I need to time constrain a source-synchronous interface between a Cyclone10GX and a LVDS camera interface running at ~596MBPS. (I'm using Quartus prime pro 19.3)
The FPGA drives out a 124MHz clk (generated by a PLL inside the FPGA) that is recovered and multiplied by 4 in the Camera by a PLL. The camera sends back 4:1 serialized data on 80 LVDS lines and a synchronous 124MHz clock. This clock is recovered in the FPGA by a PLL and serves to deserialize the input. Finally I managed to define generated clocks to describe the situation. But in the Timing analysis, the pessimism for the common clock path to the Camera PLL output is not removed, though exactly the same path is mentioned in the "Data arrival" and the "Data required" clock section (input of the base clock on Pin W24 to output of the Camera drive clock on Pin E22).
Without this common path pesimism removal the timing cannot be closed as the differences between fast and slow model over the whole path with input/PLL/output are ~2ns.
What can I do to get this pessimism removed?
You may refer to link below related to Design Guidelines for Implementing LVDS Interfaces in Cyclone Series Devices and Timing Pessimism
I know these documents and the second describes what the timing pessimism (common clock path pessimism) is and that it is removed during timing analysis. Usually there is a line in the timing analyzer report (and in the Timing analyzer GUI) that shows the removed timing pessimism. But not in this case, though both signals share most of the clock path (cf. attached file "NoPessimismRemoval.txt") . What's wrong?