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Altera_Forum
Honored Contributor I
744 Views

Close Timing on FIR filter designs in Cyclone V

Hiya All, I'm running a signal processing system employing a number of FIR filters and I am having difficulties closing timing. 

Please can anyone help me optimize my design for speed. I am running at 200 Msps with 14 bit samples, typically using 12 bit coefficients. Should I be able to implement a couple of 80 coefficient filters? Please 

Thanks 

Dave.
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4 Replies
Altera_Forum
Honored Contributor I
33 Views

Are these filters hand-built, or Altera provided? Are they symmetric, or generic? Are the taps adjustable post-synthesis or fixed? All of these questions come into play with FIR designs, and can make the difference between a design that can be implemented and one that will never meet timing. 

 

You might also find that a FIR can easily be broken into multiple FIR's operating in parallel--one on the odd samples and one on the even samples. You'd need to apply four separate FIR's to do this, assuming that you aren't adjusting your data rate--even taps applied to even samples, odd taps to even samples, even taps to odd sampless, etc. This would drop your system clock rate down to 100MHz, and might help you make timing--at the expense of twice the area. 

 

Fixed tap filters can also be easier to implement. When the tap is small, you might not need a full 14x12 bit multiply. Perhaps the tap is zero, and you don't need the tap at all. 

 

Some things to consider, 

 

Dan
Altera_Forum
Honored Contributor I
33 Views

 

--- Quote Start ---  

Are these filters hand-built, or Altera provided? Are they symmetric, or generic? Are the taps adjustable post-synthesis or fixed? All of these questions come into play with FIR designs, and can make the difference between a design that can be implemented and one that will never meet timing. 

 

You might also find that a FIR can easily be broken into multiple FIR's operating in parallel--one on the odd samples and one on the even samples. You'd need to apply four separate FIR's to do this, assuming that you aren't adjusting your data rate--even taps applied to even samples, odd taps to even samples, even taps to odd sampless, etc. This would drop your system clock rate down to 100MHz, and might help you make timing--at the expense of twice the area. 

 

Fixed tap filters can also be easier to implement. When the tap is small, you might not need a full 14x12 bit multiply. Perhaps the tap is zero, and you don't need the tap at all. 

 

Some things to consider, 

 

Dan 

--- Quote End ---  

 

 

Thanks Dan, I'm using Altera's FIR compiler II wizard. Each filter has a number of different sets of symetrical or inverse coefficients, depending on whether the filetrr is high pass or low pass. I think I can see what you are getting at with the four filter setup. I wonder why the wizard does not do that for me. Thanks a lot.  

 

While I am here I am trying to implement a high pass filter with a very low Fc in relation to the sample rate. Fc = 100KHz, with a sample rate of 200Msps. FIR does not suit (too many coefficients required) and I have not been able to get IIR to run fast enough. Ideally I need to filter out down to dc. Does anyone have any techniques I could try please? 

Dave
Altera_Forum
Honored Contributor I
33 Views

Yeah, sure ... ever tried a recursive averager (http://zipcpu.com/dsp/2017/08/19/simple-filter.html)? Such an averager can be used to filter a signal really close to DC. Subtract that from your incoming signal and you have a highpass filter. It's not FIR, it's IIR, but ... it should work nicely for you from the description you've just given. It's also *really* easy to build. I've used it in time past to remove fixed DC biases from sampled signals. 

 

Dan
Altera_Forum
Honored Contributor I
33 Views

 

--- Quote Start ---  

Yeah, sure ... ever tried a recursive averager (http://zipcpu.com/dsp/2017/08/19/simple-filter.html)? Such an averager can be used to filter a signal really close to DC. Subtract that from your incoming signal and you have a highpass filter. It's not FIR, it's IIR, but ... it should work nicely for you from the description you've just given. It's also *really* easy to build. I've used it in time past to remove fixed DC biases from sampled signals. 

 

Dan 

--- Quote End ---  

 

 

Hi Dan, I really like that idea. Thanks. I can run the averager at 100Msps and run the rest of the system at 200Msps. Nice one. 

I will let you know how I get on. Cheers Dave
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