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Hi,
I know that its not allowed to compare with 'X' or 'Z' in a synthesizable VHDL code. But is it allowed to write a code in which I compare a signal to '0' or '1' to detect an 'Z' and suspend the operation? The code is as follows: process(clk) begin if rising_edge(clk ) then if(rst = '0') then reg_0 <= (others => 'Z'); elsif(btf_start = '1') then reg_0 <= "ZZ" & frame_in; elsif(t_btf_finish = '1') then reg_0 <= (others => 'Z'); end if; end if; end process; process(clk) begin if rising_edge(clk) then if(reg_0(0) = '0' or reg_0(0) = '1') then -- DO SOME OPERATIONS else -- DO NOTHING end if; end if; end process;Link Copied
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--- Quote Start --- But is it allowed to write a code in which I compare a signal to '0' or '1' to detect an 'Z' and suspend the operation? --- Quote End --- Allowed, yes. Meaningful, no. reg_0(0) = '0' or reg_0(0) = '1' simply compiles to TRUE Consider how 'Z' state would be detected in hardware and you'll hopefully understand why the code can't work.
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Thanks for your reply.
Yes, I understood the problem. But then how does "casez" synthesize?- Mark as New
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there is no casez in VHDL.
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--- Quote Start --- there is no casez in VHDL --- Quote End --- Furthermore, the value z in Verilog casez means a don't care value for synthesis, not a test for z state. See 1364.1 ieee standard for verilog register transfer level synthesis z can't be used in compare expressions in synthesized Verilog, in so far it's the same thing as in VHDL (not surprizing).
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I think Quartus doesn't like tristate signals inside FPGA.
Tristate is for pins.- Mark as New
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I doesnt mind them - but it will convert the tristates to muxes.
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Thanks to all. Now its clear for me.
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