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Hi i am getting the following error during compilation cu any one help me plz
Error (12005): Actual width (17) of port "read_address" on instance "KIKISMDWT:UVK|dual_ram:DUALRAM" is not compatible with the formal port width (5) declared by the instantiated entity COMPONENT dual_ram IS PORT ( clock1 : IN STD_LOGIC := '1'; clock2 : IN STD_LOGIC := '1'; data : IN STD_LOGIC_VECTOR (23 DOWNTO 0); read_address : IN STD_LOGIC_VECTOR (16 DOWNTO 0); write_address : IN STD_LOGIC_VECTOR (16 DOWNTO 0); wren : IN STD_LOGIC := '0'; q : OUT STD_LOGIC_VECTOR (23 DOWNTO 0) ); END COMPONENT; DUALRAM : dual_ram PORT MAP(clock1,clock2,data,read_address,write_address,wren,q);Link Copied
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You didnt post the entity, but the error suggests your component doesnt match the entity definition. You need to fix the component to match the entity, or forget about components completely and use direct instantiation:
DUALRAM : entity library_where_ram_is_compiled.dual_ram
port map (
--etc
)
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As the message says, your 'read_address' signal has probably a width of 5 instead of the expected width of 17
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