Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Compilation fail duo to hps_csdram_p0

davidyu1
Beginner
1,775 Views

We used platform designer and use hps IP to build our design.

But Compilation failed and had the following message:

Error: The auto-constraining script was not able to detect any instance for core < hps_sdram_p0 >
Error: Verify the following:
Error: The core < hps_sdram_p0 > is instantiated within another component (wrapper)
Error: The core is not the top-level of the project
Error: The memory interface pins are exported to the top-level of the project
Error: Alternatively, if you are no longer instantiating core < hps_sdram_p0 >,
Error: clean up any stale SDC_FILE references from the QSF/QIP files.

 

How to solve this issue?

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11 Replies
sstrell
Honored Contributor III
1,732 Views

Is this a golden reference design you downloaded or something you created yourself?  Can you show the Platform Designer system design (.qsys)?

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davidyu1
Beginner
1,675 Views

@sstrell I created new project with "DE10_Nano_golden_top" template to design our FPGA SoC.

I have attached .qsys file to this post.

 

 

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david711205
Beginner
1,620 Views

@sstrell Any suggestion about this issue?

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aikeu
Employee
1,555 Views

Hi davidyu1,


Do you still require help regarding this issue?


Thanks.

Regards,

Aik Eu


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davidyu1
Beginner
1,546 Views

Yes, I still need help.

 

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aikeu
Employee
1,510 Views

Hi davidyu1,


May I know which document which you refer to build your project?

The original ghrd used was working fine without compilation issue or after you modify it only got issue?


Thanks.

Regards,

Aik Eu


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davidyu1
Beginner
1,506 Views
Hi Aik Eu,
I created new project with your de10-nano template file(DE10_Nano_golden_top.qar) and use platform designer to add hps-to-fpga interface in my design.
You can see my project files I attached the post previously.
I found that the compilation issue is from adding hps-to-fpga interface.
If I remove hps-to-fpga interface from qsys, the compilation is without error.
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aikeu
Employee
1,445 Views

Hi davidyu1,


I am referring to this link:

https://gist.github.com/addisonElliott/8c229e47184a724d1a00328110dc094c

Under Building the project, there are a few steps before step 7 which you might need to perform after you have compile your qsys design in order to avoid the errors.


Thanks.

Regards,

Aik Eu


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davidyu1
Beginner
1,431 Views

Hi Aik Eu,

When I followed these steps from the link you metioned, running hps_sdram_p0_pin_assignments.tcl had the similar error.

I have attached the screen shot file to the post.

 

Thanks.

Regards,

David Yu

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aikeu
Employee
1,420 Views

Hi davidyu1,


I understand that you have modified the golden design example of DE10 nano. I not very sure the problem from your modification other than adding additional soft IP which connect to the bridge.

Anway can try run with other example like from previous link or any example which uses a PIO controller IP:

https://www.rocketboards.org/foswiki/Documentation/SoCEDS

From there only add on your modification.


Thanks.

Regards,

Aik Eu


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aikeu
Employee
1,370 Views

Hi davidyu1,


I am closing this thread now. Do consider re-open a new thread after you have tried the compilation with a working pio design example.


Thanks.

Regards,

Aik Eu


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