Intel Quartus 18.1 Build 625 compilation freezes at 2% when code snippet below is present in the Verilog code.
I have modified the code VGA_Pattern project provided with DE10-Lite to load hex RGB data from a file and during the display interval it shall access the data_ROM at a dynamic index that incrments on every horizontal synch interval.
The Array has been defined as per below.
reg [7:0] data_ROM [0:(3*640*480)-1]; initial begin $readmemh("vgah.mem", data_ROM); end
I tried several variants to access to access the data form the data_ROM but the compiler keeps looping at 2%.
I see error below:
Error (10054): Verilog HDL File I/O error at vga_controller.v(51): can't open Verilog Design File "vgah.mem"
The vgah.mem file is missing. Could you provide this file?
Upon checking, this is caused by the .mem file where the Intel Quartus Prime software cannot read the information in this file. Could you recreate the memory initialization (.mif) file for the ROM? Please let me know if the problem persists.
I think the size of the memory may not be appropriate for the MAX 10 FPGA. I will change the project to use the SDRAM then I can initialize it with the RGB. That should hopefully work.