Compiler Problem

[Altera_Forum]

Dear all, 

 Device : max II.  The module function is to latch to 1 at the SignalIn risign edge. The code1 works well. As you know, there is an internal reset signal in MAX II device. so we don't need to reset to 0; So I write code 2, it works well in modelsim, but it will not work in Quartus. In quartus , the bit is always 1. The reason is that quartus will optimize and will not see the default reset action.  So, how can i make the code 2 work correctly? perhaps iis there an option used to cahnge compiler action?  thanks;)  /////////////////////////////////////////// // code 1 /////////////////////////////////////////// input wire nrst; output reg bit;  always @ (negedge nrst, posedge signalin)  if (!nrst)  bit <= 0;  else   bit <= 1;  /////////////////////////////////////////// // code 2 /////////////////////////////////////////// output reg bit; always @ (posedge signalin)  bit <= 1;

[Altera_Forum]

--- Quote Start ---  Dear all,  Device : max II.  The module function is to latch to 1 at the SignalIn risign edge. The code1 works well. As you know, there is an internal reset signal in MAX II device. so we don't need to reset to 0; So I write code 2, it works well in modelsim, but it will not work in Quartus. In quartus , the bit is always 1. The reason is that quartus will optimize and will not see the default reset action.  So, how can i make the code 2 work correctly? perhaps iis there an option used to cahnge compiler action?  thanks;)  /////////////////////////////////////////// // code 1 /////////////////////////////////////////// input wire nrst; output reg bit;  always @ (negedge nrst, posedge signalin)  if (!nrst)  bit <= 0;  else   bit <= 1;  /////////////////////////////////////////// // code 2 /////////////////////////////////////////// output reg bit; always @ (posedge signalin)  bit <= 1;  --- Quote End ---    code 1 has reset, code 2 has no reset so what is the problem.  The global powerup reset has nothing to do with code.

[Altera_Forum]

try to turn off option for synthesis "Power up register with don't care value 'X'" <- it is default value. 

but it is better do all signal assignments explicit, as pointed out by Kaz.

[Altera_Forum]

--- Quote Start ---  try to turn off option for synthesis "Power up register with don't care value 'X'" <- it is default value. but it is better do all signal assignments explicit, as pointed out by Kaz.  --- Quote End ---    I think the OP is about the difference between code1 and code2 cases.  code1) if you apply reset (in code) then assign value on clock edge you are asking for a register even though in this case it is waste because the signal is assigned '1' all the way through. So the compiler here is not that clever, wastes register and creates timing path.  code2) If you don't apply reset but just clock edge assignment then compiler gets clever and says you don't need register and so wires your signal to a constant and ignores clock edge assignment.  The conclusion is that if you have constants do not apply reset and so do not create registers and timing paths.

[Altera_Forum]

:) but i think the OP is about inconsistent in simualtion and synthesis. 

Cause I don't like Verilog i never check before for "Ignore Verilog initial constructs" for synthesis. so when writing code for synthesis you should take in considaration some synthesis options and make assignment for it accordingly. but if one want to power-up with '1' in register -> one should look for template in quartus text-editor.

[Altera_Forum]

--- Quote Start ---  :) but i think the OP is about inconsistent in simualtion and synthesis. Cause I don't like Verilog i never check before for "Ignore Verilog initial constructs" for synthesis. so when writing code for synthesis you should take in considaration some synthesis options and make assignment for it accordingly. but if one want to power-up with '1' in register -> one should look for template in quartus text-editor.  --- Quote End ---    Yes, Modelsim follows your code virtually line by line. Synthesis does not as it has optimisation rules. My description above applies to synthesis be it VHDL or verilog.  If you have a constant you don't need register and so you don't need powerup value.   What I am saying is that if you apply reset followed by clock edge the synthesis respects your assignment, creates register and so is equivalent to modelsim. If you don't apply reset it does not (and issues warning) unless you ask to keep that using attributes to override the synthesis rules.

[Altera_Forum]

The practical advantage of this discussion can be illustrated below: 

 Suppose you have 50 constant coefficients each 16 bits, If you get registers you are wasting 800 registers plus creating 800 setup/hold paths + 800 recovery/removal paths. If you get them on wires you only require some routing, no registers, no timing paths, same performance. Which is better?  If you applied reset and clked process you get registers. if you apply clked process, tool ignores registers if you apply reset but comment out assignment you get 800 latches, even worse.

[Altera_Forum]

So, what does hjz007 expect at the very end: simple playing with toy or serious project? (both the same - without serious preparation you can not get simplicity). 

He/she able to make good decision after that.