Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)

Concatenation in VHDL

Altera_Forum
Honored Contributor II
7,300 Views

Hi, 

 

I have a question and maybe you can help me. I am writing a code in VHDL and I came across the following problem: 

 

I have a four-bit input, ranging from 0 to 9 with time, called "Hundreds" and need to concatenate it with the following string: "100011". I wonder if the following code snippet work: 

 

 

"100011"&hundreds; 

 

 

If you do not work, how do I solve this problem? 

 

 

Thank you
0 Kudos
7 Replies
Altera_Forum
Honored Contributor II
5,857 Views

Without seeing the full code, we will have no idea. Why not try some code and compiling it?

0 Kudos
Altera_Forum
Honored Contributor II
5,857 Views

Sorry... Below is the code: 

 

 

 

LIBRARY ieee; 

USE ieee.std_logic_1164.all; 

 

ENTITY dados_lcd IS 

PORT( 

clk : IN STD_LOGIC; --system clock 

hundreds : IN STD_LOGIC_VECTOR(3 DOWNTO 0); 

tens : IN STD_LOGIC_VECTOR(3 DOWNTO 0); 

unit : IN STD_LOGIC_VECTOR(3 DOWNTO 0); 

rw, rs, e : OUT STD_LOGIC; --read/write, setup/data, and enable for lcd 

lcd_data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); --data signals for lcd 

END dados_lcd; 

 

ARCHITECTURE behavioral OF dados_lcd IS 

SIGNAL lcd_enable : STD_LOGIC; 

SIGNAL lcd_bus : STD_LOGIC_VECTOR(9 DOWNTO 0); 

SIGNAL lcd_busy : STD_LOGIC; 

COMPONENT lcd_controller IS 

PORT( 

clk : IN STD_LOGIC; --system clock 

reset_n : IN STD_LOGIC; --active low reinitializes lcd 

lcd_enable : IN STD_LOGIC; --latches data into lcd controller 

lcd_bus : IN STD_LOGIC_VECTOR(9 DOWNTO 0); --data and control signals 

busy : OUT STD_LOGIC; --lcd controller busy/idle feedback 

rw, rs, e : OUT STD_LOGIC; --read/write, setup/data, and enable for lcd 

lcd_data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); --data signals for lcd 

END COMPONENT; 

BEGIN 

 

--instanciando o lcd_controller 

dados: lcd_controller 

PORT MAP(clk => clk,  

reset_n => '1',  

lcd_enable => lcd_enable,  

lcd_bus => lcd_bus,  

busy => lcd_busy,  

rw => rw,  

rs => rs,  

e => e,  

lcd_data => lcd_data 

); 

 

PROCESS(clk, hundreds, tens, unit) 

VARIABLE char : INTEGER RANGE 0 TO 25 := 0; 

BEGIN 

IF(clk'EVENT AND clk = '1') THEN 

IF(lcd_busy = '0' AND lcd_enable = '0') THEN 

lcd_enable <= '1'; 

IF(char < 25) THEN 

char := char + 1; 

END IF; 

CASE char IS 

WHEN 1 => lcd_bus <= "1001000100"; --D 

WHEN 2 => lcd_bus <= "1001001001"; --I 

WHEN 3 => lcd_bus <= "1001010011"; --S 

WHEN 4 => lcd_bus <= "1001010100"; --T 

WHEN 5 => lcd_bus <= "1010110110"; -- 

WHEN 6 => lcd_bus <= "1001001110"; --N 

WHEN 7 => lcd_bus <= "1001000011"; --C 

WHEN 8 => lcd_bus <= "1001001001"; --I 

WHEN 9 => lcd_bus <= "1001000001"; --A 

WHEN 10 => lcd_bus <= "1000111010"; --: 

WHEN 11 => lcd_bus <= "0011000000"; --Command (cursor primeira posição da segunda linha) 

WHEN 12 => lcd_bus <= "1000100000"; --SPC 

WHEN 13 => lcd_bus <= "1000100000"; --SPC 

WHEN 14 => lcd_bus <= "1000100000"; --SPC 

WHEN 15 => lcd_bus <= "1000100000"; --SPC 

WHEN 16 => lcd_bus <= "1000100000"; --SPC 

WHEN 17 => lcd_bus <= "1000100000"; --SPC 

WHEN 18 => lcd_bus <= "1000100000"; --SPC 

WHEN 19 => lcd_bus <= "1000100000"; --SPC 

WHEN 20 => lcd_bus <= "1000100000"; --SPC 

WHEN 21 => lcd_bus <= "1000100000"; --SPC 

WHEN 22 => lcd_bus <= "100011"&hundreds; --centenas 

WHEN 23 => lcd_bus <= "100011"&tens; --dezenas 

WHEN 24 => lcd_bus <= "100011"&unit; --unidades 

WHEN OTHERS => lcd_enable <= '0'; 

END CASE; 

ELSE 

lcd_enable <= '0'; 

END IF; 

END IF; 

END PROCESS; 

END behavioral;
0 Kudos
Altera_Forum
Honored Contributor II
5,857 Views

And whats the problem?

0 Kudos
Altera_Forum
Honored Contributor II
5,857 Views

My question is whether it is right to do the following: 

 

"100011"&hundreds 

 

When "Hundreds" equals "1001", the result will be: "100011"&"1001" = "1000111001" ? 

 

Thanks
0 Kudos
Altera_Forum
Honored Contributor II
5,857 Views

These kind of questions can quickly and easily be checked with a compiler and simulator (quicker than using a forum) 

 

Yes, this is exactly how it works.
0 Kudos
Altera_Forum
Honored Contributor II
5,857 Views

Ok, thank you and apologize for the inconvenience.

0 Kudos
Altera_Forum
Honored Contributor II
5,857 Views

You can try using Modelsim Altera Starter edition which is free to simulation the functional behavior of your logic.

0 Kudos
Reply