Condition when in vhdl code

[Altera_Forum]

Sorry for my bad english, 

I have a problem in my code: i use the function  case x is when y => but instead of a value i would like to have something (>= Y) i don't know if it's possible but if not how can i change it ? I can also link my code to let you see it. Thanks, Renaud

[Altera_Forum]

The values in when statements must be constants known at compile time.

[Altera_Forum]

So it won't work if i do this: 

case cnt => when (>= 80) =>  leds <= "0001";  if(cnt > 90)  leds <= "0011";  end if; when(...) end case

[Altera_Forum]

Case statements are for explicit constant values and need to cover all cases. If your want to use compare functions you must use an if statement.

[Altera_Forum]

how can i improve this to have less logical elements ? 

if((cnt >= 80) and (cnt < 90)) then   leds_s <= "01";  leds_g <= "0000";  leds_f <= "00";  elsif(cnt >= 90) then  leds_s <= "11";  leds_g <= "0000";  leds_f <= "00";  elsif((cnt <= 18) and (cnt > 16)) then   leds_f <= "01";  leds_g <= "0000";  leds_s <= "00";  elsif(cnt <= 16) then  leds_f <= "11";  leds_g <= "0000";  leds_s <= "00";  elsif((cnt < 80) and (cnt >= 42)) then   leds_s <= "00";  leds_g <= "0001";  leds_f <= "00";  elsif((cnt < 42) and (cnt >= 29)) then  leds_s <= "00";  leds_g <= "0011";  leds_f <= "00";  elsif((cnt < 29) and (cnt >= 22)) then  leds_s <= "00";  leds_g <= "0111";  leds_f <= "00";  else  leds_s <= "11";  leds_g <= "1111";  leds_f <= "00";  end if;

[Altera_Forum]

Avoid using the elsif construct. It will create long logic chains that cannot execute in one clock cycle unless your clock is slow. You seem to have the same values assigned in multiple blocks. Try structuring it as as series of conditions for each variable separately. Remember, all of your logic will execute at the same time.

[Altera_Forum]

--- Quote Start ---  Avoid using the elsif construct. It will create long logic chains that cannot execute in one clock cycle unless your clock is slow. You seem to have the same values assigned in multiple blocks. Try structuring it as as series of conditions for each variable separately. Remember, all of your logic will execute at the same time.  --- Quote End ---    I would avoid the use of the word"execute". This implies software. A better phrase would be "logic that fails timing checks".  But I do agree, you're better of separating the signals to have their own if sections. But other than that you can't really simplify it.

[Altera_Forum]

Indeed i have to simulate an electrocardiogram with 2 inputs (clk and hearts) and show the number of bpm with 8 leds (Very slow, slow, good1, good2,good3,good4, fast, very fast) 

my clock is equal to 60 Hz and i use the value i want for hearts and my leds turn on according the number of bpm.  I have key value : 45 bpm is slow, < 35 VS, 200 fast 210 VF, and good1,...,good4 are between 45 and 200 (almost equal). I had a previous code for 2 leds (slow and fast) but if i use the same process i have too many LE. How can I make it out ?  I hope you understand everything because i don't speak english very well. Thanks

[Altera_Forum]

What fpga are you using, your code shouldn't use too many les. Can you pretty the code? Also, 60hz clock seems a little strange, how do you generate this clock? Usual and recommended method us to use the system clock with 60hz enable

[Altera_Forum]

I use the cpld 5M80ZE64C5. We had a lab at university and we had to do some experiment(like I said before with 2leds). Also our PCB has 2 clocks, from our datasheet we could see that we had one clock is 0.7 Hz to 48 and the other is 59 to 320 Hz. We had to choose the second clock and we took a small frequency(60). We had a work to do (with 8 leds) that use less than 22 LE and we have minus if we have more than 25. I link codes i tried and the first one for 2 leds (cardio.vhd) 

This is one of my first project so i hope you understand it is not very good. Thanks   PS : don't mind commentaries (i'm belgian so i speak french :) )