Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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I'm trying to test "Low Latency 40G and 40GBASE-KR4 MAC & PHY" IPCore. Instantiation of a core in Platform designer shows an IP which have only "Conduit" type outputs. no clocks no buses, nothing.
Hi,
Yes, I can observe the same. The IP is currently need to connect from the top level of the design. You may generate the example design to get more information of the connection.
Regard -SK
