Configuring the Quartus IP library "RS232 UART, CLK signal

[JMona1]

I am trying to add the Quartus IP library "RS232 UART" into a .bdf file.

Seems to load fine but during the "Generate" I get an error "The input clock frequency must be known at generation time." How do I supply the clock frequency. (I have a 50Mhz clock going to a pin on the FPGA) can I somehow use this?

Please Help really need an answer on this to get going..

Thanks

[Vicky1]

Hi,

You can use Platform Designer(Qsys) to generate the Block symbol file(.bsf) and that you can use into .bdf file.

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards

Vikas Jathar 

(This message was posted on behalf of Intel Corporation)

[JMona1]

Thanks Vicky for the suggestion. Unfortunately I’m a complete newbie to Quartus. Coming from a KiCAD board design background I want to program FPGAs using .bdf files. (To me Verilog is like programming Web pages by hand in HTML rather than a web page editor).

Anyway, I have a few real basic questions that will hopefully be useful to other new users…

First I don’t understand your answer/suggestion. Sorry.

What I want to do is add a simple old fashioned UART to a board. The University Program|communications “RS232 UART” seems to be exactly what I want. I can in fact get it to my main “FPGA_IO_Board.bdf” window as a block diagram. All the inputs I can provide except I don’t know how to supply the CLK.

I want to run it at say 9600 BAUD. Can I just use my main FPGA clock input pin (50MHz) and via a PLL & counter supply the frequency X16.

The UART parameter Editor gave an error when generating the Verilog saying the clk was undefined. That’s the only error I got. If I supply it (and of course connect up all the other inputs) should the .bdf box work?

BTW I don’t (think) I have the NEOS CPU active/present. I don’t need it for this application. Some of the documentation seems to refer to it. Totally unclear docs to a new user!

[JMona1]

How does one launch the Platform Designer (Qsys) within Quartus Prime (V18)

[Vicky1]

Hi,

In Quartus Prime (V18) Go to Tools -> Platform Designer.

Seems to load fine but during the "Generate" I get an error "The input clock frequency must be known at generation time."

Check the below KDB link,

https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/ip/2018/error--rs232_0--the-input-clock-frequency-must-be-known-at-gener.html

For Baud rate setting refer the below link,

ftp://ftp.altera.com/up/pub/Intel_Material/16.1/University_Program_IP_Cores/Communication/RS232.pdf

Best Regards

Vikas Jathar 

(This message was posted on behalf of Intel Corporation)

[JMona1]

Thanks Vicky, I did see that info. I guess I should rephrase my question. Can I just ignore the Platform Designer Error described above and just go ahead an provide the baud rate frequency myself (as described in the article you identified). Will it work then?

[Vicky1]

Hi,

Yes, It should work but if you come across any issue related to clock then you have add the "RS232 UART instance"  in top design module.

Best Regards

Vikas Jathar 

(This message was posted on behalf of Intel Corporation)

[JMona1]

Thanks for help Vicky