Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
15465 Discussions

Confused about myriad of AXI to Avalon bridge options


Hi all,


I am having a hard time choosing the correct type of bridge component for our IP (AXI4 interface, with both a master and slave interface). What is the difference between the "AXI Bridge Intel FPGA IP" and "AXI Translator Intel FPGA IP"? They seem to have very similar interfaces and options. I'm wondering if one of these is preferable to the other.


Basically I want to have CSRs written by user software go to my IP's slave interface, and the IP master interface makes AXI read/write requests.


Also, if there were any example designs for PCIe HIP + MSGDMA + AXI/Avalon bus translator, that would be great!

0 Kudos
1 Reply

Hi, the tutorial video in the link below could help answer some of your inquiries:

AMBA AXI and Altera Avalon Interoperation using Qsys (now called platform designer)