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Confused about myriad of AXI to Avalon bridge options

Hi all,

 

I am having a hard time choosing the correct type of bridge component for our IP (AXI4 interface, with both a master and slave interface). What is the difference between the "AXI Bridge Intel FPGA IP" and "AXI Translator Intel FPGA IP"? They seem to have very similar interfaces and options. I'm wondering if one of these is preferable to the other.

 

Basically I want to have CSRs written by user software go to my IP's slave interface, and the IP master interface makes AXI read/write requests.

 

Also, if there were any example designs for PCIe HIP + MSGDMA + AXI/Avalon bus translator, that would be great!

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Hi, the tutorial video in the link below could help answer some of your inquiries:

AMBA AXI and Altera Avalon Interoperation using Qsys (now called platform designer)

https://www.youtube.com/watch?v=LdD2B1x-5vo

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