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Altera_Forum
Honored Contributor I
2,000 Views

Connect split bus in verilog to output

Hello, 

 

I believe this is a really easy question, but I have searched how to do it for a long time and I still can't figure it out. I am just now switching from VHDL to verilog. 

 

I want to connect parts of the module to an output(the problem is with data_out): 

 

module Tau2_LVDS( rx_inclock, rx_in, rx_outclock, data_out, sync_frame_start, sync_line_valid, sync_data_invalid ); input rx_inclock; input rx_in; output rx_outclock; output data_out; output sync_frame_start; output sync_line_valid; output sync_data_invalid; wire rx_inclock; wire rx_in; wire rx_outclock; wire data_out; wire sync_frame_start; wire sync_line_valid; sync_data_invalid; wire rx_out_wire; wire sync_decode_signal; assign rx_out_wire=data_out; tau2_sync_decode sync_decoder_inst( .sync_in(rx_out_wire), .sync_frame_start(sync_frame_start), .sync_line_valid(sync_line_valid), .sync_data_invalid(sync_data_invalid) ); tau2_lvds_deser tau2_lvds_deser_inst( .rx_in(rx_in), .rx_inclock(rx_inclock), .rx_out(rx_out_wire), .rx_outclock(rx_outclock) ); endmodule  

 

However, when I view the circuit in the RTL viewer, rx_out and data_out are not connected. 

 

In VHDL the code used for this would look like this: 

PORT MAP(rx_inclock => rx_inclock, rx_in => rx_in, rx_outclock => rx_outclock, rx_out(20 DOWNTO 7) => data_out(13 DOWNTO 0), rx_out(6 DOWNTO 0) => sync_decode_signal(6 DOWNTO 0), ); 

 

I just can't figure out either how the verilog connections are constructed, it is quite confusing. In VHDL, when you connect something to the module in/output with =>, it is connected, end of story. Here the roles of the module ports are defined outside of the module definition, but still somehow automatically connected, and then these are somehow also automatically connected to the wires with the wires of the same name, or so it seems, except this output I try to connect. Could someone help me with this? :)
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2 Replies
Altera_Forum
Honored Contributor I
308 Views

you could always used name association, rather than inplied association (which is confusing as you have found) 

 

my_module inst_my_module ( .rx_in( rx_in ), .rx_outclock( rx_outclock ), .rx_out( { data_out, sync_decode_signal } ) ... etc );  

 

Also, why not be more explicit with your ports. Your code uses Verilog95 style. This was updated in 2001 to be more like VHDL (and much easier to follow): 

 

module Tau2_LVDS( input rx_inclock; input rx_in; output rx_outclock; output data_out; output sync_frame_start; output sync_line_valid; output sync_data_invalid; );
Altera_Forum
Honored Contributor I
308 Views

Thank you very much, it works, now :) It is also much simpler and logical. For anyone stumbling upon this question the final code is: 

 

module Tau2_LVDS( input rx_inclock, input rx_in, output rx_outclock, output data_out, output sync_frame_start, output sync_line_valid, output sync_data_invalid ); wire sync_decode_signal; tau2_sync_decode sync_decoder_inst( .sync_in(sync_decode_signal), .sync_frame_start(sync_frame_start), .sync_line_valid(sync_line_valid), .sync_data_invalid(sync_data_invalid) ); tau2_lvds_deser tau2_lvds_deser_inst( .rx_in(rx_in), .rx_inclock(rx_inclock), .rx_out( {data_out, sync_decode_signal }), .rx_outclock(rx_outclock) ); endmodule