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Connecting Problem of UniPHY DDR2 Megawizard Pins to FPGA Pins

Altera_Forum
Honored Contributor II
1,066 Views

Hello, 

 

I am trying to connect generated Megawizard for DDR2 800 1GB SODIMM to appropriate pins on a board similar to Terasic DE3 board. Memory is MT8HTF12864HDZ, I took configuration for MT8HTF12864AZ and change 3->2 clocks, 1->2 ranks. 

 

Pins for all addr/dq/dqs... are allocated and many times verified. 

 

If I connect oct_rdn and oct_rup I obtain ca 2500 Errors like 

 

Error (174068): Output buffer atom "my_ddr2:my_ddr2_module|my_ddr2_0002:my_ddr2_inst|my_ddr2_p0:p0|my_ddr2_p0_memphy:umemphy|my_ddr2_p0_new_io_pads:uio_pads|my_ddr2_p0_altdqdqs:dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|obuf_os_bar_0" has port "PARALLELTERMINATIONCONTROL[13]" connected, but does not use calibrated on-chip termination 

 

if I skip this connection - I receive only few errors of the following type: 

 

Error (15700): Termination calibration block atom "my_ddr2:my_ddr2_module|my_ddr2_0002:my_ddr2_inst|altera_mem_if_oct_stratixiv:oct0|sd1a_0" uses RUP port, which must be connected to an I/O atom in input mode 

 

I found several threads in the Alteraforum with similar problem, but, there is no solution for this problem. Below I print my portions of main Verilog file and pin assigments. 

 

Please, adwise me what to do! 

 

Thank you! 

 

Ilghiz 

 

verilog module: 

module FPGA_Top_Level( // other assignments... output mem_a, // memory.mem_a | SSTL-18 Class I output mem_ba, // .mem_ba | SSTL-18 Class I output mem_ck, // .mem_ck | Differential 1.8-V SSTL Class I output mem_ck_n, // .mem_ck_n | Differential 1.8-V SSTL Class I output mem_cke, // .mem_cke | SSTL-18 Class I output mem_cs_n, // .mem_cs_n | SSTL-18 Class I output mem_dm, // .mem_dm | SSTL-18 Class I output mem_ras_n, // .mem_ras_n | SSTL-18 Class I output mem_cas_n, // .mem_cas_n | SSTL-18 Class I output mem_we_n, // .mem_we_n | SSTL-18 Class I inout mem_dq, // .mem_dq | SSTL-18 Class I inout mem_dqs, // .mem_dqs | Differential 1.8-V SSTL Class I inout mem_dqs_n, // .mem_dqs_n | Differential 1.8-V SSTL Class I output mem_odt, // .mem_odt | SSTL-18 Class I // input oct_rdn, // oct.rdn input oct_rup // .rup ); //.... my_ddr2 my_ddr2_module( .pll_ref_clk (pll_ref_clk), // pll_ref_clk.clk .global_reset_n (reset_n), // global_reset.reset_n .soft_reset_n (reset_n), // soft_reset.reset_n .afi_clk (afi_clk), // afi_clk.clk .afi_half_clk (afi_half_clk), // afi_half_clk.clk .afi_reset_n (afi_reset_n), // afi_reset.reset_n .afi_reset_export_n(afi_reset_export_n), // afi_reset_export.reset_n .mem_a (mem_a), // memory.mem_a .mem_ba (mem_ba), // .mem_ba .mem_ck (mem_ck), // .mem_ck .mem_ck_n (mem_ck_n), // .mem_ck_n .mem_cke (mem_cke), // .mem_cke .mem_cs_n (mem_cs_n), // .mem_cs_n .mem_dm (mem_dm), // .mem_dm .mem_ras_n (mem_ras_n), // .mem_ras_n .mem_cas_n (mem_cas_n), // .mem_cas_n .mem_we_n (mem_we_n), // .mem_we_n .mem_dq (mem_dq), // .mem_dq .mem_dqs (mem_dqs), // .mem_dqs .mem_dqs_n (mem_dqs_n), // .mem_dqs_n .mem_odt (mem_odt), // .mem_odt .avl_ready (avl_ready), // avl.waitrequest_n .avl_burstbegin (avl_burstbegin), // .beginbursttransfer .avl_addr (avl_addr), // .address .avl_rdata_valid (avl_rdata_valid), // .readdatavalid .avl_rdata (avl_rdata), // .readdata .avl_wdata (avl_wdata), // .writedata .avl_be (avl_be), // .byteenable .avl_read_req (avl_read_req), // .read .avl_write_req (avl_write_req), // .write .avl_size (avl_size), // .burstcount .local_init_done (local_init_done), // status.local_init_done .local_cal_success (local_cal_success), // .local_cal_success .local_cal_fail (local_cal_fail), // .local_cal_fail .oct_rdn (oct_rdn), // oct.rdn .oct_rup (oct_rup) // .rup ); endmodule  

 

pin assigments: 

set_location_assignment PIN_... -to mem_dq set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to mem_dq set_location_assignment PIN_... -to mem_a set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to mem_a set_location_assignment PIN_... -to mem_dqs set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to mem_dqs set_location_assignment PIN_... -to mem_dqs_n set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to mem_dqs_n set_location_assignment PIN_... -to mem_dm set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to mem_dm set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to mem_odt set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to mem_odt set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to mem_ras_n set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to mem_we_n set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to mem_ba set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to mem_ba set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to mem_ba set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to mem_cas_n set_location_assignment PIN_AF14 -to mem_ba set_location_assignment PIN_AF15 -to mem_ba set_location_assignment PIN_AE15 -to mem_ba set_location_assignment PIN_AD17 -to mem_cas_n set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to mem_ck set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to mem_ck set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to mem_ck_n set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to mem_ck_n set_location_assignment PIN_AE16 -to mem_ck set_location_assignment PIN_AF16 -to mem_ck_n set_location_assignment PIN_AH16 -to mem_ck set_location_assignment PIN_AJ15 -to mem_ck_n set_location_assignment PIN_AM18 -to mem_odt set_location_assignment PIN_AG15 -to mem_odt set_location_assignment PIN_AE17 -to mem_ras_n set_location_assignment PIN_AF17 -to mem_we_n set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to mem_cke set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to mem_cs_n set_location_assignment PIN_AJ12 -to mem_cke set_location_assignment PIN_AK17 -to mem_cs_n set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to mem_cke set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to mem_cs_n set_location_assignment PIN_AJ20 -to mem_cke set_location_assignment PIN_AL18 -to mem_cs_n set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to oct_rup set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to oct_rdn set_location_assignment PIN_AL28 -to oct_rup set_location_assignment PIN_AK29 -to oct_rdn
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3 Replies
Altera_Forum
Honored Contributor II
182 Views

You are missing constraints from your project's settings file (.qsf). You need to run the appropriate .tcl file, from within Quartus, to fill out the .qsf, with parameters appropriate to the memory specified in your project. 

 

From within Quartus, under 'Tools', click on 'Tcl Scripts...'. 

 

Providing you've compiled your project once (which you must have done given the results you've posted), the window that comes up will populate itself with a number of tcl scripts appropriate to your project. These will include scripts for configuring your DDR2 memory pinouts and parameters. Running these will add the appropriate settings to your project, after which your project should complile more successfully. 

 

Regards, 

Alex
Altera_Forum
Honored Contributor II
182 Views

Dear Alex, 

 

thank you for your simple solution! It works now!!! 

 

Sincerely, 

 

Ilghiz
Altera_Forum
Honored Contributor II
182 Views

Dear Alex, 

 

Thanks for the solution. 

 

Regards, 

Krishna
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