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Valued Contributor III
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Constrained clock appears as unconstrained input

Hello, 

 

I've spent a considerable amount of time several months ago to look into timing constraint issues, but had never understood how it works ... all this staff, despite several manuals I looked through. 

Then I abandoned it in favour of other things. 

Recently I returned to that work, and once more face these issues. 

So here is my constraint file - it was generated by Terasic System Builder and then I added some additional instructions, in particular, create_clock and create_generated_clock

Timing Analysis reports 2 violations: one unconstrained input port and on unconstrained output port. 

 

CLOCK_50 No input delay, min/max delays, false-path exceptions, or max skew assignments found. This port has clock assignment. 

DRAM_CLK No output delay, min/max delays, false-path exceptions, or max skew assignments found. This port has clock assignment. 

 

But input port is part of create_clock instruction, so must be considered as constrained, and output port is part of create_generated_clock instruction, so also must be considered as constrained (if my comprehension is correct). 

Where I've been mistaken ? 

Thanks in advance. 

 

#**************************************************************# This .sdc file is created by Terasic Tool.# Users are recommended to modify this file to match users logic.# ************************************************************** # **************************************************************# Create Clock# ************************************************************** create_clock -period 20.0 -name clk CLOCK_50 create_clock -period 20.0 -name clk_dram# create_clock -period "100 MHz" -name clk_dram # for enhancing USB BlasterII to be reliable, 25MHz create_clock -name {altera_reserved_tck} -period 40 {altera_reserved_tck} set_input_delay -clock altera_reserved_tck -clock_fall 3 set_input_delay -clock altera_reserved_tck -clock_fall 3 set_output_delay -clock altera_reserved_tck 3 # **************************************************************# Create Generated Clock# ************************************************************** create_generated_clock -name clk_sdram_ext -source # derive_pll_clocks # **************************************************************# Set Clock Latency# ************************************************************* # **************************************************************# Set Clock Uncertainty# ************************************************************** derive_clock_uncertainty # **************************************************************# Set Input Delay# **************************************************************# Board Delay (Data) + Propagation Delay - Board Delay (Clock) set_input_delay -max -clock clk_dram -0.048 set_input_delay -min -clock clk_dram -0.057 # **************************************************************# Set Output Delay# **************************************************************# max : Board Delay (Data) - Board Delay (Clock) + tsu (External Device)# min : Board Delay (Data) - Board Delay (Clock) - th (External Device) set_output_delay -max -clock clk_dram 1.452 set_output_delay -min -clock clk_dram -0.857 set_output_delay -max -clock clk_dram 1.531 set_output_delay -min -clock clk_dram -0.805 set_output_delay -max -clock clk_dram 1.533 set_output_delay -min -clock clk_dram -0.805 set_output_delay -max -clock clk_dram 1.510 set_output_delay -min -clock clk_dram -0.800 set_output_delay -max -clock clk_dram 1.520 set_output_delay -min -clock clk_dram -0.780 set_output_delay -max -clock clk_dram 1.5000 set_output_delay -min -clock clk_dram -0.800 set_output_delay -max -clock clk_dram 1.545 set_output_delay -min -clock clk_dram -0.755 set_output_delay -max -clock clk_dram 1.496 set_output_delay -min -clock clk_dram -0.804 set_output_delay -max -clock clk_dram 1.508 set_output_delay -min -clock clk_dram -0.792 # **************************************************************# Set Clock Groups# ************************************************************** # **************************************************************# Set False Path# ************************************************************** set_false_path -from set_false_path -from set_false_path -from * -to set_false_path -from * -to
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Valued Contributor III
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Hi, 

 

If I understand you correctly, your PLD receives the reference clock at the CLOCK_50 pin, and internally routes that pin to the DRAM_CLK output pin; all external logic receives its clock from the PLD's DRAM_CLK pin. 

 

These changes should fix your warnings: 

... create_clock -period 20.0 -name clk # create_clock -period 20.0 -name clk_dram ... create_generated_clock -name clk_dram -source ... 

 

The first statement defines a logical clock named "clk", which comes from the pin "CLOCK_50". You already had that, but I'm not sure if it really works without "get_ports()", so I added that. 

 

The second statement is, as far as I understand it, wrong, so I commented it out. 

 

The third statement defines another logical clock, named "clk_dram", which is basically the same as "clk", but measured with pin "DRAM_CLK" as a reference. I fixed the name of the clock that it generates. 

 

Below that, there should be all your set_xyz_delay statements, where you already use the clock name "clk_dram". 

 

Hope that helps. 

- GooGooCluster
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Valued Contributor III
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Thank you GooGooCluster, 

 

I've just tried your suggestions. 

Unfortunately the result is the same - timing analysis reports two unconstrained ports - clock_50 and dram_clk

 

 

--- Quote Start ---  

If I understand you correctly, your PLD receives the reference clock at the CLOCK_50 pin, and internally routes that pin to the DRAM_CLK output pin; all external logic receives its clock from the PLD's DRAM_CLK pin. 

--- Quote End ---  

 

Yes, the FPGA (Cyclon V) receives 50MHz clock (generated on the board) at clock_50

Then this clock is "redirected" (assign DRAM_CLK = CLOCK_50) to clock external SDRAM chip. 

Concerning other SDRAM staff (i.e. DRAM_***), all these ports are clocked by the clock, derived from main system clock (i.e. CLOCK_50), as these interface ports are "created" by inserting the "SDRAM controller IP" in Qsys. 

 

I used a virtual clock for creating input/output delays for SDRAM staff, which you suggested to comment (i.e.# create_clock -period 20.0 -name clk_dram) because in all manuals that I'v seen until now it's this "mysterious object", named virtual clock, that is used for creating input/output delays. In the same time in all these manuals, the clock for external module is generated outside FPGA, whereas in my case (and I think in majority cases, it's FPGA, that delivers clock for external module). 

So, I consider your suggestion as quite reasonable, but unfortunately it didn't help ... probably due to some option improperly set somewhere. 

 

Regards.
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Valued Contributor III
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I've found the same problem in this thread (April 2012) 

 

http://alterauserforums.net/forum/showthread.php?t=37111&p=153235 

 

... isn't resolved since 5.5 years !!!
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Valued Contributor III
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Finally I've found the source of problem. 

It's caused by assign dram_clk = clock_50 assignment. 

When I comment it, timing analysis passes without reporting unconstrained input/output. 

But I still need to "redirect" system clock clock_50 to dram_clk to clock external SDRAM chip. 

I've tried buf(dram_clk, clock_50) instead of assign dram_clk = clock_50 ... and problem reappeared. 

Any suggestions ?
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Valued Contributor III
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You should probably use a PLL to generate DRAM_CLK instead of just trying to route it through.

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Valued Contributor III
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Yes, I know that with PLL it works, but actually I'm trying to do without PLL, as board manufacturer states that at 50MHz no phase shift needed between SDRAM chip clock and SDRAM controller clock. 

So is it possible without PLL ?
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Valued Contributor III
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You can set up the PLL compensation mode as a zero delay buffer. That way, it's like the PLL is basically not there.

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Valued Contributor III
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--- Quote Start ---  

Yes, I know that with PLL it works, but actually I'm trying to do without PLL, as board manufacturer states that at 50MHz no phase shift needed between SDRAM chip clock and SDRAM controller clock. 

So is it possible without PLL ? 

--- Quote End ---  

 

Yes and no... 

 

In one of my designs, I do basically that. I feed a clock into a CPLD, which is used to generate some data, which is then fed to a DAC, together with the clock (from a CPLD I/O pin). It works, but obviously the clock skew inside the CPLD will vary between compilations, even though timing closure is achieved. And I get warnings that what I'm doing is not optimum with regards to jitter. None of that matters for my application; so, yes, it can work, depending on what you want. 

 

In another design, I have an FPGA with SDR-SDRAM. Sounds more like your application. That SDRAM is more strict with regards to setup and hold time. In my case, it' was impossible to get timing closure without using a PLL that can fine-tune the clock phase. With another SDRAM controller, another SDRAM chip, another clock frequency, it might have worked without tweaking the phase. However, I have to mention that it practically works with a 180° clock phase (i.e. internally invert the clock, assume routing delay is negligible), even though the timing analyzer complains (I verified the functionality with a FSM that writes PRBS-patterns and reads them back). Why did I use a PLL then? Because that's a commercial product, where I cannot risk that some unit doesn't work because the timings hit the worst-case. 

 

In conclusion, I agree with what sstrell wrote. Use a PLL, and use it as a zero-delay buffer. Get your timing constraints to work without warnings. If a timing violation occurs, one option might be to add some phase shift with the PLL instead of doing zero-delay. 

 

Uh, well, unless you just want to play with some eval board. Then I personally would be a bit more pragmatic... you mentioned the board manufacturer's recommendation; if you have a way to verify the functionality of the SDRAM, and it just works, I would just call it a day. Sorry for ruining the fun of playing with the timing constraints then... :) 

 

But I think we drifted away from the topic a bit, didn't we? The original problem was the SDC file that complained about unconstrained paths...?
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Valued Contributor III
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I've tried with zero delay buffer: with this option PLL generates an additional output, that should be connected somewhere. I didn't understand this option and finally selected "normal" option. 

Also I din't increase PLL-generated clocks and didn't introduce phase shift. 

 

With this concept the problem didn't completely disappear - while with base clock (i.e. CLOCK_50), it's OK, DRAM_CLK still appears as unconstrained output. 

Here is fragment of Qsys: 

https://www.alteraforum.com/forum/attachment.php?attachmentid=14124  

 

And here is .sdc file: 

 

#************************************************************** # This .sdc file is created by Terasic Tool. # Users are recommended to modify this file to match users logic. # ************************************************************** # ************************************************************** # Create Clock # ************************************************************** create_clock -period 20.0 -name clk CLOCK_50 derive_pll_clocks derive_clock_uncertainty # for enhancing USB BlasterII to be reliable, 25MHz create_clock -name {altera_reserved_tck} -period 40 {altera_reserved_tck} set_input_delay -clock altera_reserved_tck -clock_fall 3 set_input_delay -clock altera_reserved_tck -clock_fall 3 set_output_delay -clock altera_reserved_tck 3 # ************************************************************** # Create Generated Clock # ************************************************************** # **** next stetement modified by GooGooCluster *** # create_generated_clock -name clk_dram -source .gpll~PLL_OUTPUT_COUNTER|divclk}] create_generated_clock -name clk_dram -source .gpll~PLL_OUTPUT_COUNTER|divclk}] # ************************************************************** # Set Input Delay # ************************************************************** # Board Delay (Data) + Propagation Delay - Board Delay (Clock) set_input_delay -max -clock clk_dram -0.048 set_input_delay -min -clock clk_dram -0.057 # ************************************************************** # Set Output Delay # ************************************************************** # max : Board Delay (Data) - Board Delay (Clock) + tsu (External Device) # min : Board Delay (Data) - Board Delay (Clock) - th (External Device) set_output_delay -max -clock clk_dram 1.452 set_output_delay -min -clock clk_dram -0.857 set_output_delay -max -clock clk_dram 1.531 set_output_delay -min -clock clk_dram -0.805 set_output_delay -max -clock clk_dram 1.533 set_output_delay -min -clock clk_dram -0.805 set_output_delay -max -clock clk_dram 1.510 set_output_delay -min -clock clk_dram -0.800 set_output_delay -max -clock clk_dram 1.520 set_output_delay -min -clock clk_dram -0.780 set_output_delay -max -clock clk_dram 1.5000 set_output_delay -min -clock clk_dram -0.800 set_output_delay -max -clock clk_dram 1.545 set_output_delay -min -clock clk_dram -0.755 set_output_delay -max -clock clk_dram 1.496 set_output_delay -min -clock clk_dram -0.804 set_output_delay -max -clock clk_dram 1.508 set_output_delay -min -clock clk_dram -0.792 # ************************************************************** # Set Clock Groups # ************************************************************** # ************************************************************** # Set False Path # ************************************************************** set_false_path -from set_false_path -from set_false_path -from * -to set_false_path -from * -to  

 

Any comments ?
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Valued Contributor III
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Mysterious ! 

 

In very similar design I did before there is no such issues. 

Short resume: 

TimeQuest analysis generates unconstrained path error on output dram_clk

This port delivers clock to external SDRAM chip and it's constrained with the following instruction: 

 

create_generated_clock -name clk_dram -source [get_pins {u0|pll|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] [get_ports {dram_clk}] 

 

Here is TimeQuest diagnostic, related to this DRAM_CLK port (setup analysis): 

 

unconstrained output ports: 

DRAM_CLK No output delay, min/max delays, false-path exceptions, or max skew assignments found. This port has clock assignment. 

 

unconstrained output port paths: 

 

 

From 

To 

From Clocks 

 

 

u0|pll|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk 

DRAM_CLK 

u0|pll|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] 

 

 

The same messages are present in hold analysis

 

Probably I've been mistaken with create_generate_clock instruction ? 

 

Thanks.
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Valued Contributor III
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I'm totally desperate  

 

I still cannot resolve this issue with unconstrained path, related to output clock. 

According to different documents, I've examined until now, the a port, that is target in create_generated_clock constraint is considered as constrained. 

... at least in multiple examples if output port serves as target in create_generated_clock constraint, there is no set_output_delay constraint for this port. 

 

Indeed, in other design that I've created some time ago and that is very similar to the actual one (I'm working on now), the identical output port isn't signaled as unconstrained. 

I'v reduced the dissimilarities of these two designs to a minimum ... I've even instantiated the qsys module from "good" design into the "bad" one. 

Does't help !!! 

 

The output port is still signaled as unconstrained. 

 

What should I check in my design to track down this mysterious issue. 

 

Thanks in advance.
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Valued Contributor III
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Output generated clock paths need to be set as false paths. The tool looks at output paths as data paths still, even though you've created a clock for it. Just false path the output clock.

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Valued Contributor III
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Thanks Sstrell, 

 

But I wonder why in another, quasi identical design, this annoying issue doesn't appear ? 

And in this design output clock isn't specified as false path.
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Valued Contributor III
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If a generated clock constraint targets an output pin, you will always see this. Perhaps there's some IP in this other design that handles it automatically for you.

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Valued Contributor III
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--- Quote Start ---  

If a generated clock constraint targets an output pin, you will always see this. Perhaps there's some IP in this other design that handles it automatically for you. 

--- Quote End ---  

 

The both designs are very simple: top level wrapping Verilog module, where is instantiated Qsys module (the same Qsys in both).
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Valued Contributor III
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Without seeing the constraints or the design, there's no way for me to know why they are different.

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Valued Contributor III
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--- Quote Start ---  

Without seeing the constraints or the design, there's no way for me to know why they are different. 

--- Quote End ---  

 

"Good" design constraints: 

create_clock -name clk -period 20 create_clock -name {altera_reserved_tck} -period 40 {altera_reserved_tck} derive_pll_clocks derive_clock_uncertainty set_input_delay -clock altera_reserved_tck -clock_fall 3 set_input_delay -clock altera_reserved_tck -clock_fall 3 set_output_delay -clock altera_reserved_tck 3 create_generated_clock -name clk_ext_sdram -source .gpll~PLL_OUTPUT_COUNTER|divclk}] # Constraint SDRAM DATA for input set_input_delay -clock clk_ext_sdram -max 6.4 ] set_input_delay -clock clk_ext_sdram -min 1.0 ] # Constraint SDRAM DATA for output set_output_delay -clock clk_ext_sdram -max 1.5 set_output_delay -clock clk_ext_sdram -min -0.8 # set_multicycle_path -setup -to }] 2# set_multicycle_path -hold -to }] 1 set_false_path -from set_false_path -from set_false_path -from * -to set_false_path -from * -to  

 

"Bad" design constraints: 

#**************************************************************# This .sdc file is created by Terasic Tool.# Users are recommended to modify this file to match users logic.# ************************************************************** # **************************************************************# Create Clock# ************************************************************** create_clock -period 20.0 -name clk CLOCK_50 # for enhancing USB BlasterII to be reliable, 25MHz create_clock -name {altera_reserved_tck} -period 40 {altera_reserved_tck} derive_pll_clocks derive_clock_uncertainty set_input_delay -clock altera_reserved_tck -clock_fall 3 set_input_delay -clock altera_reserved_tck -clock_fall 3 set_output_delay -clock altera_reserved_tck 3 # **************************************************************# Create Generated Clock# ************************************************************** create_generated_clock -name clk_sdram_ext -source .gpll~PLL_OUTPUT_COUNTER|divclk}] create_generated_clock -name clk_data -source .gpll~PLL_OUTPUT_COUNTER|divclk}] |clk}] # **************************************************************# Set Input Delay# **************************************************************# Board Delay (Data) + Propagation Delay - Board Delay (Clock) set_input_delay -clock clk_sdram_ext -max -0.048 set_input_delay -clock clk_sdram_ext -min -0.057 # **************************************************************# Set Output Delay# **************************************************************# max : Board Delay (Data) - Board Delay (Clock) + tsu (External Device)# min : Board Delay (Data) - Board Delay (Clock) - th (External Device) set_output_delay -clock clk_sdram_ext -max 1.452 set_output_delay -clock clk_sdram_ext -min -0.857 set_output_delay -clock clk_sdram_ext -max 1.531 set_output_delay -clock clk_sdram_ext -min -0.805 set_output_delay -clock clk_sdram_ext -max 1.533 set_output_delay -clock clk_sdram_ext -min -0.805 set_output_delay -clock clk_sdram_ext -max 1.510 set_output_delay -clock clk_sdram_ext -min -0.800 set_output_delay -clock clk_sdram_ext -max 1.520 set_output_delay -clock clk_sdram_ext -min -0.780 set_output_delay -clock clk_sdram_ext -max 1.5000 set_output_delay -clock clk_sdram_ext -min -0.800 set_output_delay -clock clk_sdram_ext -max 1.545 set_output_delay -clock clk_sdram_ext -min -0.755 set_output_delay -clock clk_sdram_ext -max 1.496 set_output_delay -clock clk_sdram_ext -min -0.804 set_output_delay -clock clk_sdram_ext -max 1.508 set_output_delay -clock clk_sdram_ext -min -0.792 # **************************************************************# Set False Path# ************************************************************** set_false_path -from set_false_path -from set_false_path -from * -to set_false_path -from * -to  

 

"Good" design top module 

module nios_led2_top (input clk, input sw, input key, output led_l, led_h, output hex3, hex2 , hex1, hex0, output sdram_addr, inout sdram_dq, output sdram_bank, output sdram_cas_n, sdram_ras_n, sdram_cke, sdram_cs_n, sdram_clk, output sdram_dqmh, sdram_dqml, sdram_we_n); wire sseg; assign hex3 = sseg; assign hex2 = sseg; assign hex1 = sseg; assign hex0 = sseg; nios_led2_sdram u0 ( .btn_export (key), .clk_clk (clk), .led_l_export (led_l), .led_h_export (led_h), .reset_reset_n (1'b1), .sdram_wire_addr (sdram_addr), .sdram_wire_ba (sdram_bank), .sdram_wire_cas_n (sdram_cas_n), .sdram_wire_cke (sdram_cke), .sdram_wire_cs_n (sdram_cs_n), .sdram_wire_dq (sdram_dq), .sdram_wire_dqm ({sdram_dqmh, sdram_dqml}), .sdram_wire_ras_n (sdram_ras_n), .sdram_wire_we_n (sdram_we_n), .sseg_export (sseg), .switch_export (sw), .clk_sdram_clk (sdram_clk) ); endmodule 

 

"Bad" design top module: 

//======================================================= // This code is generated by Terasic System Builder //======================================================= module ch_11( //////////// CLOCK ////////// input CLOCK_50, //////////// SDRAM ////////// output DRAM_ADDR, output DRAM_BA, output DRAM_CAS_N, output DRAM_CKE, output DRAM_CLK, output DRAM_CS_N, inout DRAM_DQ, output DRAM_LDQM, output DRAM_RAS_N, output DRAM_UDQM, output DRAM_WE_N, //////////// SEG7 ////////// output HEX0, output HEX1, output HEX2, output HEX3, //////////// KEY ////////// input KEY, //////////// LED ////////// output LEDR, //////////// SW ////////// input SW ); //======================================================= // REG/WIRE declarations //======================================================= //======================================================= // Structural coding //======================================================= // ch_11_nios u0 ( // .clk_clk (CLOCK_50), // clk.clk // .reset_reset_n (1'b1), // reset.reset_n // .switch_export (SW), // switch.export // .btn_export (KEY), // btn.export // .sseg_export ({{1'b0,HEX3},{1'b0,HEX2},{1'b0,HEX1},{1'b0,HEX0}}), // sseg.export // .sdram_addr (DRAM_ADDR), // sdram.addr // .sdram_ba (DRAM_BA), // .ba // .sdram_cas_n (DRAM_CAS_N), // .cas_n // .sdram_cke (DRAM_CKE), // .cke // .sdram_cs_n (DRAM_CS_N), // .cs_n // .sdram_dq (DRAM_DQ), // .dq // .sdram_dqm ({DRAM_UDQM, DRAM_LDQM}), // .dqm // .sdram_ras_n (DRAM_RAS_N), // .ras_n // .sdram_we_n (DRAM_WE_N), // .we_n // .led_export (LEDR), // led.export // .sdram_clk_clk (DRAM_CLK) // sdram_clk.clk // ); nios_led2_sdram u0 ( .btn_export (KEY), .clk_clk (CLOCK_50), .led_l_export (LEDR), .led_h_export (LEDR), .reset_reset_n (1'b1), .sdram_wire_addr (DRAM_ADDR), .sdram_wire_ba (DRAM_BA), .sdram_wire_cas_n (DRAM_CAS_N), .sdram_wire_cke (DRAM_CKE), .sdram_wire_cs_n (DRAM_CS_N), .sdram_wire_dq (DRAM_DQ), .sdram_wire_dqm ({DRAM_UDQM, DRAM_LDQM}), .sdram_wire_ras_n (DRAM_RAS_N), .sdram_wire_we_n (DRAM_WE_N), .sseg_export ({{1'b0,HEX3},{1'b0,HEX2},{1'b0,HEX1},{1'b0,HEX0}}), .switch_export (SW), .clk_sdram_clk (DRAM_CLK) ); endmodule 

 

Here is unconstrained output in "Bad" module: 

DRAM_CLK No output delay, min/max delays, false-path exceptions, or max skew assignments found. This port has clock assignment.
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Valued Contributor III
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In the "good" constraints, you've created a set_output_delay targeted to sdram*. Thus, this output delay constraint is covering the data output timing of this output clock, which as I mentioned, should not be constrained because you want it analyzed as a clock path, not a data path. Thus, you don't get the unconstrained path. 

 

In the "bad" constraints, you're not doing this, so DRAM_CLK appears unconstrained because it's still considered a data path.
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Valued Contributor III
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--- Quote Start ---  

In the "good" constraints, you've created a set_output_delay targeted to sdram*. Thus, this output delay constraint is covering the data output timing of this output clock, which as I mentioned, should not be constrained because you want it analyzed as a clock path, not a data path. Thus, you don't get the unconstrained path. 

 

In the "bad" constraints, you're not doing this, so DRAM_CLK appears unconstrained because it's still considered a data path. 

--- Quote End ---  

 

 

Indeed, it's the case. Thanks a lot !
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