Constraining Clock and Data Lines

[Altera_Forum]

Hi everyone. 

I have a system with an FPGA and a DAC, both fed from the same 400MHz clock source. The FPGA logic and DAC input works at 200MHz (the DAC has internal x2 interpolation, so I provide that double rate clock). I chose to operate the DAC in a mode in which I provide an interface clock (in addition to the 400MHz clock input) along with the data input to the DAC. The data is fed into a FIFO inside the DAC, and read at half the DAC's clock internaly, at the FIFO's output (once again, 200MHz). All that's left is to make sure that the data I output from the FPGA towards the DAC has an appropriate relationship to the clock which I output from the FPGA towards the DAC. Is there any option in the Classic Timing Analyzer to specify that relationship between the clock and the data?

[Altera_Forum]

Can't think of any Classic timing analyzer setting that does this - this is a typical source-synchronous scenario for which timeQuest was created. 

 Depending on what FPGA you have and how many PLL outputs you have left, there _is_ a fairly simple solution for this, but you'll have to manually inspect timing every time you do a fit. If you give me a bit more info I can probably help you do what you need to.  Best regards,    Ben

[Altera_Forum]

Thanks for the reply. 

I'm using the Stratix III 260 device, so I have 4 PLLs, one of which is dedicated to the 400MHz input. I naturally thought of what you considered, inspecting the timing of every fit and selecting an appropriate phase for a PLL output. Obviously this is a horrible solution :) I was hoping to get around that. I hadn't got used to the TimeQuest analyzer yet so I'm still sticking to the old classic one. How would you go about constraining it in the TimeQuest analyzer? If you need any specific info, I'll be delighted to share.

[Altera_Forum]

Well, let's try to keep things simple then. 

 First of all, things are easiest if the whole DAC interface is located within 1 IO bank. In that case you should give all the pins some ridiculous Tco constraint (0.5ns or so). Do a fit, see what the fitter could actually manage, and update the Tco for the DAC data pins to 0.5ns more than the results you achieved. This gives you predictable data IO timing for the data pins.  Now, of course you realize that a clock is simply a signal too. Since you have a 400MHz clock available, simply create second 400MHz output from the PLL that handles the 400MHz clock and make it drive a toggle-flipflop in your HDL of choice. Assign the output of the TFF to your DAC's data clock pin. Again, set its Tco to something ridiculous, do a fit, and update the Tco to what is achievable plus 0.5ns. This gives you reliable IO timing for the clock output.  What you can now do is adjust the phase shift of the clock toggling the TFF to match the clock/data relationship required by your DAC.  From the second fit you have obtained the phase relationship between the data and clock pins (which is the difference in Tco time between the clock and data pins). This should give you enough room to play with.  Let me know if I'm unclear at some point.  Best regards,    Ben

[Altera_Forum]

Is this solution intended for a TimeQuest constraint, or just a general solution? I thought there would be some easier way in TimeQuest, since you mentioned that TimeQuest was created to handle such problams.

[Altera_Forum]

This is intended for use with the Classic timing analyzer. 

 Timequest can do a very thorough analysis if you directly feed a PLL output to an IO pin but I personally think it's a hassle to set up (but worth the effort if you can't fit your interface into a single IO bank or using a DDR interface). Using the TFF and the Tco constraints enables you to use the Classic analyzer as well.

[Altera_Forum]

Thanks. You have been very helpful :)