Constraining LEDs/Switches to VHDL onDE1-SoC

[Altera_Forum]

Hello, I am trying to write some basic VHDL that "slide" an on led down the 10 leds on the DE1-SoC board. I have loaded the .sof onto the board but nothing is lighting up. I think the VHDL is good because I have compiled and loaded it onto a Xilinx board. I am guessing the issue is with the .sdc or .qsf files which I am given to understand constrain the code to the on-board hardware. I will post the VHDL, the .sdc, and the .qsf. 

 led_slide.vhd  library ieee;use ieee.std_logic_1164.all; entity led_slide is port( clk: in std_logic; sel: in std_logic; z: out std_logic_vector(9 downto 0) ); end led_slide; architecture Behavioral of led_slide is type my_state is ( s0, s1, s2, s3, s4, s5, s6, s7, s8, s9 ); signal n_s: my_state; signal clk_div: std_logic; begin process(clk_div) begin if clk_div='1' and clk_div'event then case n_s is when s0 => z <= "1000000000"; if sel='1' then n_s <= s1; else n_s <= s9; end if; when s1 => z <= "0100000000"; if sel='1' then n_s <= s2; else n_s <= s1; end if; when s2 => z <= "0010000000"; if sel='1' then n_s <= s3; else n_s <= s1; end if; when s3 => z <= "0001000000"; if sel='1' then n_s <= s4; else n_s <= s2; end if; when s4 => z <= "0000100000"; if sel='1' then n_s <= s5; else n_s <= s3; end if; when s5 => z <= "0000010000"; if sel='1' then n_s <= s6; else n_s <= s4; end if; when s6 => z <= "0000001000"; if sel='1' then n_s <= s7; else n_s <= s5; end if; when s7 => z <= "0000000100"; if sel='1' then n_s <= s8; else n_s <= s6; end if; when s8 => z <= "0000000010"; if sel='1' then n_s <= s9; else n_s <= s7; end if; when s9 => z <= "0000000001"; if sel='1' then n_s <= s0; else n_s <= s8; end if; end case; end if; end process; process(clk) variable count: integer; begin if clk='1' and clk'event then if count=99999 then clk_div <= not clk_div; count := 0; else count := count + 1; end if; end if; end process; end Behavioral;   de1soc_master.qsf  set_global_assignment -name FAMILY "Cyclone V" set_global_assignment -name DEVICE 5CSEMA5F31C6 set_global_assignment -name TOP_LEVEL_ENTITY "DE1_SoC" set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" set_global_assignment -name SDC_FILE led_slide.sdc # #============================================================# # LEDR# #============================================================ set_location_assignment PIN_V16 -to z set_location_assignment PIN_W16 -to z set_location_assignment PIN_V17 -to z set_location_assignment PIN_V18 -to z set_location_assignment PIN_W17 -to z set_location_assignment PIN_W19 -to z set_location_assignment PIN_Y19 -to z set_location_assignment PIN_W20 -to z set_location_assignment PIN_W21 -to z set_location_assignment PIN_Y21 -to z set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to z set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to z set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to z set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to z set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to z set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to z set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to z set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to z set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to z set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to z#   led_slide.sdc # **************************************************************# Altera DE1-SoC SDC settings# Users are recommended to modify this file to match users logic.# ************************************************************** # **************************************************************# Create Clock# ************************************************************** create_clock -period 20 create_clock -period 20 create_clock -period 20 create_clock -period 20 create_clock -period "27 MHz" -name tv_27m # VGA : 640x480@60Hz create_clock -period "25.18 MHz" -name clk_vga # **************************************************************# Create Generated Clock# ************************************************************** derive_pll_clocks # **************************************************************# Set Clock Uncertainty# ************************************************************** derive_clock_uncertainty # **************************************************************# Set Input Delay# **************************************************************# Board Delay (Data) + Propagation Delay - Board Delay (Clock) set_input_delay -max -clock clk_dram -0.048 set_input_delay -min -clock clk_dram -0.057 set_input_delay -max -clock tv_27m 3.692 set_input_delay -min -clock tv_27m 2.492 set_input_delay -max -clock tv_27m 3.654 set_input_delay -min -clock tv_27m 2.454 set_input_delay -max -clock tv_27m 3.656 set_input_delay -min -clock tv_27m 2.456 # **************************************************************# Set Output Delay# **************************************************************# max : Board Delay (Data) - Board Delay (Clock) + tsu (External Device)# min : Board Delay (Data) - Board Delay (Clock) - th (External Device) set_output_delay -max -clock clk_dram 1.452 set_output_delay -min -clock clk_dram -0.857 set_output_delay -max -clock clk_dram 1.531 set_output_delay -min -clock clk_dram -0.805 set_output_delay -max -clock clk_dram 1.533 set_output_delay -min -clock clk_dram -0.805 set_output_delay -max -clock clk_dram 1.510 set_output_delay -min -clock clk_dram -0.800 set_output_delay -max -clock clk_dram 1.520 set_output_delay -min -clock clk_dram -0.780 set_output_delay -max -clock clk_dram 1.5000 set_output_delay -min -clock clk_dram -0.800 set_output_delay -max -clock clk_dram 1.545 set_output_delay -min -clock clk_dram -0.755 set_output_delay -max -clock clk_dram 1.496 set_output_delay -min -clock clk_dram -0.804 set_output_delay -max -clock clk_dram 1.508 set_output_delay -min -clock clk_dram -0.792 set_output_delay -max -clock clk_vga 0.220 set_output_delay -min -clock clk_vga -1.506 set_output_delay -max -clock clk_vga 0.212 set_output_delay -min -clock clk_vga -1.519 set_output_delay -max -clock clk_vga 0.264 set_output_delay -min -clock clk_vga -1.519 set_output_delay -max -clock clk_vga 0.215 set_output_delay -min -clock clk_vga -1.485

[Altera_Forum]

It is clearly a problem with the constraints 

https://www.alteraforum.com/forum/attachment.php?attachmentid=15316  https://www.alteraforum.com/forum/attachment.php?attachmentid=15317  It is clear my qsf is reading the sdc because if I mess with the .sdc, it will fail to compile. I am not sure how to create and connect my VHDL clk input to a real clk  Here are the critical warnings I am seeing https://www.alteraforum.com/forum/attachment.php?attachmentid=15318

[Altera_Forum]

Hi, 

   --- Quote Start ---  I have loaded the .sof onto the board but nothing is lighting up  --- Quote End ---     You have already answered your own question.    --- Quote Start ---  I am not sure how to create and connect my VHDL clk input to a real clk  --- Quote End ---   Without clock your module will not work. Create top module with board pin names and create instance of your own module and connect board pins with your module.

[Altera_Forum]

I was able to constrain the VHDL clk, but now the tool says clk_div is unconstrained which I do not understand because it is just a clock generated based on the count of a register that is iterated by the tick of clk. Do I have to write a constraint in the sdc for this clock as well? 

 https://alteraforum.com/forum/attachment.php?attachmentid=15323&stc=1   in de1soc_master.qsf set_global_assignment -name FAMILY "Cyclone V" set_global_assignment -name DEVICE 5CSEMA5F31C6 set_global_assignment -name TOP_LEVEL_ENTITY "DE1_SoC" set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" set_global_assignment -name clk_gen.sdc# set_global_assignment -name SDC_FILE DE1_SoC.sdc  new constraint clk_gen.sdc create_clock -period 20 [get_ports clk]

[Altera_Forum]

Forget about sdc for a while. It's surely not your problem. But you absolutely need a pin assignment for the clock input. 

 Pin assignments can be comfortably entered and checked in the Pin Planner tool. Another option is to start your design using an example shipped with your DE1 board, it already has useful pin assignments for all development board signals.

[Altera_Forum]

I think you are mixing the purpose of .qsf assignments and .sdc constrains. Have you assigned clk to actual FPGA pin location and actual clk source? For now use Pin Planner from Quartus to assign actual FPGA pins to your top level ports, assign clk port to FPGA pin where is some clock source is connected (e.g oscillator).  

 After you assign pin locations your design should work (if your VHDL is good enough), even if Timequest will tell you that your design does not meet timing because tool will assume that you are running your design at 1GHz clock frequency and other stuff because there are no proper constrains.   Once you fix pin locations assignments and see some leds blinking come back here and we will solve problems with .sdc.

[Altera_Forum]

I was able to get it to work with the pin planner tool. What is the purpose of the sdc and qsf. I feel as though for a more complicated project, I will probably need those but I am not sure how they fit into Quartus.

[Altera_Forum]

A .sdc file is for defining timing requirements for a design to guide the Fitter during place and route. See this training and its follow-ons: 

 https://www.altera.com/support/training/course/odsw1115.html  .qsf is the Quartus settings file. Any assignments you create in Pin Planner or the Assignment Editor are stored there.