Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Constraints for ADC data input

New Contributor II

I have an Arria 10 connected to a Linear LTC2165 ADC capable of SDR or DDR operation.


The ADC expects a differential clock provided to time the conversion and produces a differential clock slightly later whose NEGATIVE edge coincides with the data transition in single-ended mode, and with the first of two interleaved half-words in differential DDR mode.


See attached diagrams from the LTC datasheet.  Note the flipped polarity of CLKOUT.


For a sample rate of about 104MHz, It would seem that I want constraints like:

  create_clock -name {RX_CLKp} -period 9.563 -waveform { 0.000 4.781 } {RX_CLKp} 
  set_input_delay -clock RX_CLKp -max 4.9 [get_ports {RX_D[*]}] 
  set_input_delay -clock RX_CLKp -min 4.7 [get_ports {RX_D[*]}] 

so that the data timing is aligned to the positive clock edge for Quartus to do its thing.


This doesn't seem to work.


A second question (for DDR mode) is "how do you define timing when you want to sample the data on BOTH edges of the input clock?"  Left to itself, the software will assume that no sampling happens on the negative edge and may not provide a valid sampling period there.


Note:  RX_CLKp/n uses a dedicated clock input and feeds through an alt_inbuf_diff and then a global clock control block.

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4 Replies

Hi KCMurphy,

I'm not sure about the issue that you're currently facing.

Would you like to explain a bit more about the problems?

Or is there any information that you need?



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New Contributor II

In the simplest form, we were having trouble with data from an ADC. 


All data/clock lines from ADC short and same length.  Data transitions  on falling edge of ADC-provided clock.  If the clock is 100MHz, what is the best input_delay to use?  We assumed that defining the actual clock and saying the data delay was about 1/2 the period (to account for the negative edge, would allow correct setup time calculation.  But it wasn't working.


Later we found a different reason it was not working.  But as long as I'm here, what is the proper set_input_delay method for this fairly simple setup?

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I think you may want this:

create_clock -name {RX_CLKp} -period 9.563 -waveform { 0.000 4.781 } {RX_CLKp} 
create_clock -name {RX_ADC_CLK} -period 9.563 -waveform {4.781 9.563}
set_input_delay -clock RX_ADC_CLK -max 0.0 [get_ports {RX_D[*]}] set_input_delay -clock RX__ADC_CLK -min 0.0 [get_ports {RX_D[*]}]

That creates a "virtual clock" that is sending the ADC data, and saying it is shifted by half a cycle.  (I did not look at the LT data sheet, but think you described it that way).  With this you should see a setup relationship of 4.781ns and hold relationship of -4.781ns.  What that means is if the clock and data delays in the FPGA were perfectly aligned, you would meet setup/hold slack by 4.781ns.  Another way to say it is they could skew from each other by +/-4.781ns and still meet timing.  (Though the fitter should try to align them, though having a PLL in ssync mode will help)

Next thing you need to do is account for the clock/data skew coming out of the ADC.  Let's say it's +/-2ns, and let's say the board skews are 200ps.  Then you would change the input -max value to +2.2ns and the -min value to -2.2ns.

For DDR, there is a long document I wrote a long time ago, if you want to do some reading.  Note that there are some templates you can just copy and paste from too:

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