Controlling skew between clocks

[VMots]

Hello!

Is any way to control skew between two clocks in Quartus Prime Standard 18.1.1 for Stratix V?

Thank you for any suggestion

[skyjuice]

Can you give more context? Is this a common clock transfer? If yes, make sure you use global clock network and the skew will be minimal

[VMots]

Hello!

Tank you for you answer, 

This is two clocks from one pll one precisely 2x faster than other, no phase shift for both, originally one was on global clock network second on dual regional clock network, and it produce according to timequest 400-500 ps skew between this two clock (depending on different logic lock settings).

Also I try to set this two clock to dual regional clock but result not changed 

Thank you for help again

[skyjuice]

Thanks for the info. As expected, these are cross-clock transfers causing the huge clock skew.

I suspect that the clock buffer for one of those clock networks must be located far away. You can see this through the timing report in Timing Analyzer (compare between Clock Arrival and Clock Required) and then locate them in Chip Planner for visualization.

Can you try putting them into the clock networks whose the buffers are close to each other?

[SyafieqS]

Hi Viktar,

Any updates?