Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Counter.. Having problems adding? Please help!

Altera_Forum
Honored Contributor II
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LIBRARY IEEE; 

USE IEEE.STD_LOGIC_1164.all; 

USE IEEE.STD_LOGIC_UNSIGNED.all; 

USE IEEE.STD_LOGIC_ARITH.all; 

 

ENTITY counter IS  

 

PORT(enable, clr : IN STD_LOGIC;  

THECOUNT : OUT STD_LOGIC_VECTOR(5 downto 0)); 

END counter; 

 

ARCHITECTURE a OF counter IS 

SIGNAL tmp: STD_LOGIC_VECTOR(5 downto 0); 

BEGIN 

 

PROCESS(enable, CLR) 

BEGIN 

 

IF (CLR='1') THEN 

tmp <= "000000"; 

ELSIF (enable'event and enable='1') THEN 

tmp <= tmp + 1; 

END IF; 

 

end process; 

THECOUNT <= tmp;  

end a; 

 

This is the code I am using to work a counter.. I use the simulator tool to discover that THECOUNT never increases after CLR goes low. THECOUNT is always 0. Is there something I am doing wrong? Thanks in advance for any help!
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Altera_Forum
Honored Contributor II
359 Views

Did you connect a valid clock signal on enable pin?

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Altera_Forum
Honored Contributor II
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Yes.. : / Any other ideas?

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Altera_Forum
Honored Contributor II
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Surely the problem is with simulator settings or input waveform. 

I tried to simulate your code and it works. 

I used the following stimuli: 

enable : clock signal, period 10ns 

clr : 100ns high then low 

When clr goes down, counter starts incrementing.
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