Create pin list for migration device set

[Altera_Forum]

Hi all, 

in the "Pin Migration View" of the Pin Planner it only provides limited pin function information. Is it possible to get a list which includes the general function/special function?  e.g. (Row I/O, DIFFIO_L4p, DQS0L/CQ1L,DPCLK0)  I need this so our PCB guy (using Altium) can fill in the symbol information.  He can work it out from the pin list spreadsheets but it is a lot of work (because these don't do the migration for you automatically) and quite error prone. I would rather Quartus give me a list which I know is correct.  Thanks, Dave

[Altera_Forum]

I'm not sure this is what you are looking for but.. 

 When you compile a project, Quartus produces a pin report (Fitter -> Pin-Out File) which takes into account migration devices, if you have them selected.  So, my suggestion is to - create a project and select all the migration devices - create a mock-up top level module with all the I/Os you'll need - perform pin assignment - compile the project  - cross check the PCB design with the Pin-Out File and the device pin connection gidelines

[Altera_Forum]

Ideally what I want is a way to generate a tabular list of every pin on a given migration device "set" including the general purpose AND special function names for every pin on the device. NOT the user assigned function (which is what the pin file provides). 

 Given such a list, it would be straightforward to import the pin names into Altium or any other design software.  In my case, the migration set happens to be Cyclone IV EP4CE6E22, EP4CE10E22, EP4CE15E22, EP4CE22E22.  I'm running 9.1 SP2 - I'm not sure if later version of Quartus have made this possible.

[Altera_Forum]

Hi De-em: 

 I've been asking for something like this for years, but Altera has yet to get it.  To me, they should provide a "Migration pin out" and if possible a symbol for popular schematic software based on the device package.  I know as a FPGA designer, the first thing we need after the spec, is a board, the last thing we have is the complete functionality, and management always wants up to fit more logic into a smaller device.  What I want to be able to do is get a board quickly with the largest device possible in that package, then at the end of the design, when cost matters, be able to migrate it into the smallest device and know it will work with the original board, even if I didn't have "Migrate device" clicked.  How I work around this, is I take the excel pinout files, and merge all the various parts together into one master pinout then compare functionality pin by pin to insure I get all the variables understood.  It's a long process, and there are device family rules that can kill you even it you get it all right.  I'm currently working on the Cyclone V design, and "Device Migration" is not possible, because all the family members are not available yet, and the pinout available is useless, because it only lists the 150k LE Family members right now.  I've already found a tone of pins in the 300k LE part that are unavailable, by playing with the beta version of Quartus 12.   If they provided a "Migration pin-out" I could at least go forward with the board with some hope of migration compatibility.   Sorry this really wasn't an answer to your question, but thanks for bringing it up.  Pete    Pete

[Altera_Forum]

--- Quote Start ---  Ideally what I want is a way to generate a tabular list of every pin on a given migration device "set" including the general purpose AND special function names for every pin on the device. NOT the user assigned function (which is what the pin file provides).  --- Quote End ---    It provides a bit more than that.  It says what each and every pin in the package is for your specific project and project settings (migration devices, configuration scheme, unused pins options, etc). Not only for user I/Os, but for every pin -- unused pins, JTAG, VCCs, GNDs, VREFs, NCs, etc.  And that includes migration related stuff. For example, the compilation checks that the pins you've assigned signals can be used as I/Os in all the devices. Another example, if you have a pin which is NC in one device but VREF on another device, it will show up as VREF in the pin-out file if you select both devices.  Granted, it's not what you want when you're designing a PCB and trying to find out the simplest way to route to the FPGA. For that, I'd try to merge the spreadsheets and use some filters to remove the non-interesting pins.  But as a correctness check that you haven't made an error and designed a PCB with a un-workable pin out, the pin-out report it's invaluable IMHO.

[Altera_Forum]

Logged with Altera Service Request 10863182 

 Response from Altera: "There isn't any additional information supplied in 11.1. I will pass on your comments for consideration in a future Quartus version."