Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
16238 Discussions

Cross Talk of LVDS Pin from SE IO is too high




I am creating a project for the Cyclone V A5 F23 device, I am using all true lvds receiver pins in bank 3B and 4A. I have added other control single ended IO to both bank 3B and 4A but am getting this warning:


Critical Warning (12888): Cross talk of LVDS Pin lvds_rxda[0] from SE IO is too high.

Reassign or move one or more of the following SE I/Os pins location and re-run the analysis again. 

Please refer to the guideline from the Knowledge Base solution ID: rd10102013_979 and ensure the total % of crosstalk for the following SE I/O pins does not exceed 100%.


   Info (12899): SE I/O from the bank contributed to 45.64% of the margin due to SSN

   Info (12900): SE I/O spare_lvltl[0] contributed to 20.72% of margin due to crosstalk

   Info (12900): SE I/O tp_gen[3] contributed to 8.28% of margin due to crosstalk

   Info (12900): SE I/O tp_gen[2] contributed to 12.65% of margin due to crosstalk

   Info (12900): SE I/O tp_gen[1] contributed to 7.42% of margin due to crosstalk

   Info (12900): SE I/O tp_gen[0] contributed to 18.48% of margin due to crosstalk


Firstly the warning states to keep the total % crosstalk for SSN should be less than 100%, the warning says the SE IO in the bank contributed 45.64% which is less than 100?


I have followed the KDB article (the excel to show you which pins to keep out of is hopeless to use by the way!) and the SE IO pins I have placed are at least 1 pin away from all LVDS signals but I still get the warning.


How should I proceed? Do I have to use the set max toggle rate assignment? which seems like a bit of a hack.


I am running Quartus Prime V15.1.2 build 193 standard edition.




0 Kudos
1 Reply

Hi ,

Can you please try the auto placement option.




0 Kudos