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Custom Built Avalon IP generating waitRequest but not being honored in the Interconnect.

ThomasTessier
New Contributor I
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I have a simple ArriaV based design using Quartus 21.1 that has a JTAG Master and BFM Master (for simulation).  I am using a custom SPI module design that has a simple Avalon Slave interface.  In my IP and my ip_hw.tcl I have the waitRequest listed as a slave signal.

When simulating this I can see my IP generated waitRequest is not making it o the BFM Master. Other Altera IP are generating this signals and propagating it to the BFM Master.

What are the required "properties" and "attributes" in the ip_hw.tcl file that request this connectivity from the Interconnect Builder?

The IP has: package require -exact qsys 14.0 as it baseline.

Thanks,

TomT...

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ShengN_Intel
Employee
1,058 Views

Hi,

 

Check this Avalon® Verification IP Suite Design Example https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/horizontal/exm-avalon-verification-ip.html. Check design avlmm_1x1_verilog_test.

Below attached the design example avlm_avls_1x1_hw.tcl and simulation waveform. Make sure there's nothing missing or mismatch. In order to simulate with BFM Master, you may have to refer to Avalon-MM Slave BFM.

 

Thanks,

Best Regards,

Sheng

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer.

 

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sstrell
Honored Contributor III
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When you say that waitrequest is "not making it" to the host, what do you mean?  Can you show your simulation waveform?

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ThomasTessier
New Contributor I
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ThomasTessier_0-1681142363468.png

 

The Blue Circle is showing wait_request occurring at the Avalon Master BFM when I read/write to an Altera GPIO block.

The Red Circle is showing my custom SPI controller generating wait_request but it never makes it to the Avalon Master BFM pins.

TomT...

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sstrell
Honored Contributor III
983 Views

(Using the new terminology below: host=master, agent=slave)

The interconnect may not be passing the waitrequest to the host because the host is not trying to access your agent component if I'm looking at the simulation correctly.  There's no need for the interconnect to stall the host from accessing your agent if the host is not actively trying to access your agent.  Remember waitrequest input to a host completely stalls the host.  If the host wants/needs to access other agents, the interconnect is not going to stall it even if a particular agents is manually asserting waitrequest.

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ShengN_Intel
Employee
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Hi,

 

Compared the posted simulation with the design example simulation (check image below), I noticed there're some differences between slave_write (posted simulation) and avs_write (design example simulation). The avm_waitrequest will be asserted and avm_writedata will only begin transferred during REQ_WRITE (write request) where avm_write will be '1'.

ShengN_Intel_0-1681293540582.png

 

Thanks,

Best Regards,

Sheng

 

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ShengN_Intel
Employee
897 Views

Hi,

 

One more thing is make sure there's proper wire connection between avm_waitrequest and slave_waitrequest like the .v file attached below. For example,

.avm_waitrequest    (master_0_m0_waitrequest),

...

.avs_waitrequest     (master_0_m0_waitrequest),

Similar problem is encountered if there's no proper wire connection.

 

Thanks,

Sheng

 

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