Customize pattern generator created in Qsys

[Altera_Forum]

I did a design for Stratix V GX FPGA in order to transmit 3 independent channels. This design was created using qsys, also the pattern generator and the pattern_checker were created in qsys. Now I need introduce my own binary sequence but the pattern generator created by qsys just let you choose between PRBS_7, PRBS_15, PRBS_23, PRBS_31, HIGH_FREQ and LOW_FREQ. Is it possible introduce my own stream in a module created by qsys? Any idea? or should I need to create an external pattern generator programming it by verilog? Do you know if it would be possible load a file with my sequence of 1's and 0's from the PC to the FPGA?  

 Thanks you!

[Altera_Forum]

--- Quote Start ---  Is it possible introduce my own stream in a module created by qsys? Any idea? or should I need to create an external pattern generator programming it by verilog? Do you know if it would be possible load a file with my sequence of 1's and 0's from the PC to the FPGA?    --- Quote End ---    One option for a custom pattern generator is to use dual-port RAM. The pattern is then cyclic, with a maximum cycle length the size of the RAM (or smaller if you make it programmable). You can access one port of the RAM from Qsys, and the other from custom logic.  For the pattern generators I've written, I also have an Avalon-MM slave interface to control registers, so that I can enable and disable the pattern, and access bit-error-rate counters, etc.  Its easy to load the RAM from your PC if you use a JTAG-to-Avalon-MM bridge, eg., see this tutorial:  http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial  Cheers, Dave

[Altera_Forum]

Thank you very much for your help Dave, I am gonna read the tutorial and I let you know if I finally get it. 

 Cheers,  Raquel

[Altera_Forum]

I have tried to replace the pattern generator by a dual-port ram, then I have made the same connections in qsys as the pattern, the problem is my pattern generator has an avalon streaming source connected to a timing adapter, so I would need to connect the avalon memory mapped slave (S2) to the timing adapter like a source, but the design doesn´t let me the connection because it is a slave not a source. Moreover the clock1 has been connected to the general clock, clock2 has been connected to the protocol low_latency and s1 to the master. Is it that correct?  

In my design I had a data_pattern_checker as well, Is it possible leave this interface in order to control the registers once I have replaced the data_pattern_generator by onchip_memory 2_0?  Thank you.

[Altera_Forum]

--- Quote Start ---  the problem is my pattern generator has an avalon streaming source connected to a timing adapter   --- Quote End ---   Why? A dual-port RAM can use two independent clocks, so your Avalon-ST source interface should not require a different clock than the sink, so you should not need a timing adapter.    --- Quote Start ---   In my design I had a data_pattern_checker as well, Is it possible leave this interface in order to control the registers once I have replaced the data_pattern_generator by onchip_memory 2_0?   --- Quote End ---   Sure. Use SignalTap II to look at your pattern generator, or better yet, simulate the whole thing in Modelsim first.  Cheers, Dave

[Altera_Forum]

In my current design, the pattern_out of the pattern generator is connected to a timing_adapter and the out of the timing adapter is connected tx_parallel_data of the low_latency protocol. This is a design for a "Transceiver Toolkit". But now I have replaced the pattern generator by an on-chip RAM but actually I don't know very well how I should to connect the RAM in this design. I attached my current qsys system in order to make more understandable. 

Maybe should I change my design?   Thank you for your help.

[Altera_Forum]

Sorry, I don't have time to help you design your system. You just have to take the time to understand all the concepts. 

 Ignore your design for the moment, and decide what components you need. Create those components and instantiate them in a Qsys system with the verification IP test components. Write a Modelsim simulation and check your components work.  Only then can you add them to a system.   Once you create a system with Altera and your IP, then create a testbench and test it.  The key is to get everything working in Modelsim first. In Modelsim you have much better visibility into the design. If you cannot get things to work in Modelsim, what chance do you have of getting it to work in real hardware?  Cheers, Dave

[Altera_Forum]

Anyway, thank you very much for your help Dave. This design works perfect, but I have no way to customize the pattern generator and unfortunately I have no time to think of another design to transmit to 12.5 Gbps. So I really appreciate any suggestion of anybody. 

 Thank you!

[Altera_Forum]

Any help? Finally I have changed the design and I have created all the modules in megawizard connecting them to the master avalon bridge in qsys using an slave, furthermore I have created a PRBS where you can choose between PRBS 7, PRBS 15 or fix data, the problem is the width is only 40 bits. Actually I have a text file with 10^9 bits that I would like to introduce as my pattern. Is it possible with a dual-port ram introduce that number of bits? How would I be able to read the text file and introduce them as my input bitstream? 

 Thanks

[Altera_Forum]

--- Quote Start ---  I have a text file with 10^9 bits that I would like to introduce as my pattern. Is it possible with a dual-port ram introduce that number of bits? How would I be able to read the text file and introduce them as my input bitstream?  --- Quote End ---    10^9 = 1Gbit, is about 1000x too big for on-chip RAM. However, it is only 128MB which is not bad for DDR memory. Ultimately it depends on what your hardware has to offer.  Regarding using Avalon-MM/Avalon-ST RAM components, I have recently updated a tutorial that contains these components;  http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-104paper_hawkins.pdf  The PDF has links to the code.   Cheers, Dave

[Altera_Forum]

Thank you Dave, 

 I have a question about the avalon_to_st_ram. In my case I want to initialize the RAM with a .mif file. In this case I think I don't need a FIFO, right? because I want to create a .mif fixed that it will be my pattern and I want that this .mif repeats every time. Or should my xcvr_low_latency_phy read from a fifo instead of the RAM directly? if I initialize my RAM, It is not necessary a dual-clock, isn't it?   I really appreciate your help.

[Altera_Forum]

--- Quote Start ---   I have a question about the avalon_to_st_ram. In my case I want to initialize the RAM with a .mif file. In this case I think I don't need a FIFO, right? because I want to create a .mif fixed that it will be my pattern and I want that this .mif repeats every time. Or should my xcvr_low_latency_phy read from a fifo instead of the RAM directly? if I initialize my RAM, It is not necessary a dual-clock, isn't it?    --- Quote End ---   Sure, if you want a fixed pattern, and that pattern can fit in on-chip RAM, then you can use a single-ported RAM initialized from a .mif file and use a single clock domain.  However, if you've ever had to debug a system, you'll realize that one pattern is generally not enough :)  For example, I only have a 1GHz scope, so when looking at 5Gbps and 10Gbps lanes, I load a RAM pattern that repeats at a much lower frequency, eg., a square-wave.  Your system design should always include an option for debug access, eg., a JTAG connector, so having an option to load the RAM does not "cost" much.  Cheers, Dave

[Altera_Forum]

Hello again, 

 Finally, I have decided to make another design. This consists in a qsys system with a clock system, a ref. clock, a jtag to avalon master bridge and 3 external slave interfaces ( 1 exports avalon signals to interface with Low_Latency PHY core, another exports to the Reconfiguration Controller and the last exports to a RAM-2ports). All of that modules have been created using Megawizard. I have started with a RAM-2port of 32 words x 8 bit with a single clock and I have initialized with a .mif file. The content of this .mif file is what i want to get in the output of one of the channels of the Stratix V transceivers (transmitting to 2,5 Gbps) i.e. I would like the content of this file that consists in binary sequence is continually repeated. This design compiles and load in the board without any problem, but when I test the signal in the DSO it seems I am transmitting just the clock signal, that means that my protocol low_latency is not reading from my dual_port RAM. Any idea how could I fix this problem?  Thank you!

[Altera_Forum]

--- Quote Start ---   Any idea how could I fix this problem?   --- Quote End ---    You should first simulate the design :)  Cheers, Dave

[Altera_Forum]

Thanks Dave, Could you give some advices how can I simulate? I am really new in simulations, actually I am new working with FPGAs :).  

Which simulation tool would be the best for simulate this design? Modelsim? Should I simulate every block separately? Should I simulate only the memory?Do you know any manual for beginners?  Thanks

[Altera_Forum]

--- Quote Start ---  Could you give some advices how can I simulate?   --- Quote End ---    Sure, go through this tutorial, it simulates most of what you are using;  http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial  Note that Altera have changed the format of the Modelsim setup_sim.tcl script they create for simulating their IP in the latest version of the tools, so use exactly the version of Quartus I use in the tutorial. Once you have the tutorial working, you can move to the newer version of the tools and figure out the differences. I'll update the tutorial for version 12.1sp1 and 13.0 when I get time, but that is not now :)  Cheers, Dave