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Hello, for my project, i need to generate an input that is customizable. Means that i want to customize the high state and low state. For example, I set 1 sec for high state and 0.5 sec for low state. How can i set this kind of signal from vhdl ? Any ideas ? Thank you in advance.
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use a counter to count out 1s and 0.5s. Then toggle.
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what do you mean by toggling both counter ?
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Use a counter to count out the time. Then set your signal as you want at the appropriate time.
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D you have any example ?
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signal cnt : unsigned(31 downto 0);
process(clk)
begin
if rising_edge(clk) then
cnt <= cnt + 1;
if cnt = ONE_S then
op <= '1';
elsif cnt = ONE_S_PLUS_0_5s then
op <= '0';
end if;
end if;
end process;
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Thank you !
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Do I need a loop for this signal to repeat infinitely ?
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--- Quote Start ---
signal cnt : unsigned(31 downto 0);
process(clk)
begin
cnt <= cnt + 1;
if cnt = ONE_S then
op <= '1';
elsif cnt = ONE_S_PLUS_0_5s then
op <= '0';
end if;
end process;
--- Quote End --- Tricky, I am a bit disappointed...no clocking this time
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--- Quote Start --- Do I need a loop for this signal to repeat infinitely ? --- Quote End --- No, it is a continuous logic by itself but you need to add clock edge and your counter will keep going for ever.
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--- Quote Start --- Tricky, I am a bit disappointed...no clocking this time --- Quote End --- Doh - fixed it.
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