Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Altera_Forum
Honored Contributor I
1,003 Views

Customized signal

Hello, for my project, i need to generate an input that is customizable. Means that i want to customize the high state and low state. For example, I set 1 sec for high state and 0.5 sec for low state. How can i set this kind of signal from vhdl ? Any ideas ? Thank you in advance.

0 Kudos
10 Replies
Altera_Forum
Honored Contributor I
86 Views

use a counter to count out 1s and 0.5s. Then toggle.

Altera_Forum
Honored Contributor I
86 Views

what do you mean by toggling both counter ?

Altera_Forum
Honored Contributor I
86 Views

Use a counter to count out the time. Then set your signal as you want at the appropriate time.

Altera_Forum
Honored Contributor I
86 Views

D you have any example ?

Altera_Forum
Honored Contributor I
86 Views

signal cnt : unsigned(31 downto 0); process(clk) begin if rising_edge(clk) then cnt <= cnt + 1; if cnt = ONE_S then op <= '1'; elsif cnt = ONE_S_PLUS_0_5s then op <= '0'; end if; end if; end process;

Altera_Forum
Honored Contributor I
86 Views

Thank you !

Altera_Forum
Honored Contributor I
86 Views

Do I need a loop for this signal to repeat infinitely ?

Altera_Forum
Honored Contributor I
86 Views

 

--- Quote Start ---  

signal cnt : unsigned(31 downto 0); process(clk) begin cnt <= cnt + 1; if cnt = ONE_S then op <= '1'; elsif cnt = ONE_S_PLUS_0_5s then op <= '0'; end if; end process;  

--- Quote End ---  

 

 

Tricky, I am a bit disappointed...no clocking this time
Altera_Forum
Honored Contributor I
86 Views

 

--- Quote Start ---  

Do I need a loop for this signal to repeat infinitely ? 

--- Quote End ---  

 

 

No, it is a continuous logic by itself but you need to add clock edge and your counter will keep going for ever.
Altera_Forum
Honored Contributor I
86 Views

 

--- Quote Start ---  

Tricky, I am a bit disappointed...no clocking this time 

--- Quote End ---  

 

 

Doh - fixed it.
Reply