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14943 Discussions

Cyclone 10GX Transceiver TX and RX independent

Visshnu
Beginner
412 Views

Hi,

I am trying the cyclone 10gx low latency 10G base-R MAC example design(which comes with the duplex TX and RX mode)with the transceiver in TX and RX independent mode. When I try to merge the TX and RX  with the following commands:

set_instance_assignment -name XCVR_RECONFIG_GROUP 1 -to rx_serial_data[1] -entity altera_eth_top
set_instance_assignment -name XCVR_RECONFIG_GROUP 1 -to tx_serial_data[1] -entity altera_eth_top

set_instance_assignment -name XCVR_RECONFIG_GROUP 0 -to tx_serial_data[0] -entity altera_eth_top
set_instance_assignment -name XCVR_RECONFIG_GROUP 0 -to rx_serial_data[0] -entity altera_eth_top

set_instance_assignment -name XCVR_RECONFIG_GROUP 0 -to altera_eth_top:altera_eth_top_inst|TX*twentynm_hssi_avmm_if_inst*
set_instance_assignment -name XCVR_RECONFIG_GROUP 0 -to  "altera_eth_top:altera_eth_top_inst|RX*twentynm_hssi_avmm_if_inst*" -entity altera_eth_top

The project compiles but during  hardware testing,the no of good packets as well as bad packets is zero. What has to be done to merge the TX and RX in this example design.

 

 

0 Kudos
1 Solution
Deshi_Intel
Moderator
313 Views

Sorry, I forgot to attach the designs in earlier post

View solution in original post

14 Replies
Deshi_Intel
Moderator
398 Views

HI,


Can you let me know which example design that you are referring here ?

  • Any URL link to download the example design or how do you generate the example design ?


Also, I presume you are testing using C10 GX dev kit board or your own board ?

  • Does the example design hardware test passed without modification on the qsf file setting ?


Thanks.


Regards,

dlim


Visshnu
Beginner
392 Views

i used the document from the link below and created the example design

https://www.intel.com/content/www/us/en/programmable/documentation/dbf1520991817584.html

The example used transceiver in duplex mode but i wanted to try tx and rx in simplex mode.i created a tx and rx  ip separately  using the same ip parameters and used it in the altera_eth_wrapper. I am trying to understand the working of the transceiver .

Yes i am using cyclone 10gx dev kit(10CX220YF780E5G) .The example design passed the hardware test without  any modifications .

Deshi_Intel
Moderator
380 Views

Hi,


May I know why you want to break the duplex channel into simplex channel ?


Other than using the XCVR_RECONFIG_GROUP qsf command that you shown earlier, you also need to take care of the overlap address mapping. You can refer to below KDB link for more detail.


You may need to modify the example design accordingly to remap back correct address space. This could be one the of the reason that explained failure in your side.


Thanks.


Regards,

dlim



Visshnu
Beginner
365 Views

hi,

thanks for the kdb article ,I am currently trying to understand the working of the Transceiver and wanted to know how it would work if set in simplex mode. In the altera_eth_base_r_wrapper.v file   i have set the tx and rx pins  as 

.reconfig_clk (csr_clk),
.reconfig_reset (~csr_rst_n),
.reconfig_write (phy_csr_write),
.reconfig_read (phy_csr_read),
.reconfig_address (phy_csr_address),
.reconfig_writedata (phy_csr_writedata),

When i tried this the the same issue occurs .Is this the right way to do it or should i change it in the platform designer?

Deshi_Intel
Moderator
361 Views

HI,


Did you change it in just your RTL design ?


I think it's better if you follow the KDB workaround guideline to modify the design in platform designer

  • The goal is to merge the address space for both Tx and Rx together


Thanks.


Regards,

dlim


Visshnu
Beginner
353 Views

Hi ,

In the qsys file ,i have added the TX and RX ip files and an Avalon pipeline bridge ip. In the platform designer ,gave the same wire level expressions as in the KDB article .Now another issue occurs 

Error(12829): Failed to merge HSSI Avalon Memory-Mapped interface instances "dut_inst|CHANNEL[0].wrapper_inst|u0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst" and "dut_inst|CHANNEL[0].wrapper_inst|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst" into single Avalon Memory-Mapped Interface.
Error(12829): Failed to merge HSSI Avalon Memory-Mapped interface instances "dut_inst|CHANNEL[1].wrapper_inst|u0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst" and "dut_inst|CHANNEL[1].wrapper_inst|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst" into single Avalon Memory-Mapped Interface.

What is the workaround for this issue??

Deshi_Intel
Moderator
340 Views

HI,


Let me try to check around to see if I can find example design to showcase to you how to merge simplex channel.


Thanks.


Regards,

dlim


Deshi_Intel
Moderator
339 Views

HI,


Also may I know which Quartus version that you used ?


Have you tried with at least v19.4 and onwards ?


Thanks.


Regards,

Deshi


Visshnu
Beginner
335 Views

Hi, 

I am using 20.2 version Quartus  Pro edition .

 

Deshi_Intel
Moderator
318 Views

channel merging rule.png

Simplex channel merge design requirement

Deshi_Intel
Moderator
316 Views

I created 2 example design based on above design requirement and it did pass fitter compilation

  • Ensure both Tx simplex and Rx simplex reconfig interface connect to same design source 
  • Set both Tx and Rx pins to same Avalon MM group name
  1. My first example design is with "wire expression" connection in QSYS
  2. while my second example design is without " wire expression" connection in QSYS 

Both designs are able to pass fitter compilation

Thanks.

Regards,

dlim

Deshi_Intel
Moderator
314 Views

Sorry, I forgot to attach the designs in earlier post

View solution in original post

Deshi_Intel
Moderator
312 Views

You can now compare and cross check with your design


PVanL
Novice
179 Views

Hi Deshi, i worked with Visshnu on this subject for his internship, and he is now proceeding to his masters. Unfortunately, we didn't ,manage to map your design including our PHY design, to the cyclone.

The simulation works though, with the xcvr_x1_plb_s0 (Avalon-MM interface, readdata, writedata etc...) signals unconnected. I don't understand what the purpose of those signals are: The tx_parallel [63:0] signal carries the to-be-send signal, the tx_tx_serial signal carries the serial output, whereas rx_rx_serial receives the incoming signal, and the rx_rx_parallel[63:0]  carries the received parallel data...For what do you then need this Avalon-MM interface?

Also, i am not really sure what we mean with simplex. My interpretation is: There is a channel[0], on the end of which there is a trcvr[0] with a tx channel. That channel is connected via the 10Gbps cable to the rx-channel of the trcvr[1] in channel[1]. Simplex as: there is only one channel, carrying traffic in one direction. Of course not very useful in normal datacommuncation, but more simple, and using less LU's.

A duplex system would then be:

A: there is a channel[0], with a tx_trcvr[0], connected via the 10gbps cable to rx_trcvr[1] in channel[1], AND a channel[1] with tx_trcvr[1], connected via the same cable, but different pair, to the rx_trcvr[0], to channel[0],

OR:

B: there is a channel[0], with a tx_trcvr[0], connected via the FMC card to rx_trcvr[0] in channel[0]

Please advise,

regards, Pieter

 

 

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