Cyclone III ALTPLL without extclk port

[Altera_Forum]

Hi, 

 I'm using Quartus II 9v1 (web edition) with the Cyclone III Starter Board. When I set the clock output of the PLL to the corresponding output pin of the device, I get the warning message:  "pll_main_clk:inst1|altpll:altpll_component|pll_main_clk_altpll:auto_generated|pll1" output port clk[3] feeds output pin "SSRAM_CLK~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance.  What should I do that the warning message don't appear the next time I compile? The ALTPLL megafunction don't offer me an external clock output for the PLL.  Regards,  Matthias

[Altera_Forum]

Hi, 

 I think the problem is, that only output port C0 of the PLL can directly drive the dedicated external clock output. All other outputs must use a GCLK to drive the pin.  Regards, HJS