Cyclone V IOB Register Packing

[NJackson]

Warning (176225): Can't pack node OEM_Prototype_Top_Level:TOP_LEVEL|TX_Signal_Path:TX_Signal_Path_inst|Stave_ADC_CTRL:IIU_ADC_CTRL_inst|LTC2380_CTRL:\CHANNEL:1:LTC2380_CTRL_INST|adc_sr[0] to I/O pin
Warning (176229): Can't pack node OEM_Prototype_Top_Level:TOP_LEVEL|TX_Signal_Path:TX_Signal_Path_inst|Stave_ADC_CTRL:IIU_ADC_CTRL_inst|LTC2380_CTRL:\CHANNEL:1:LTC2380_CTRL_INST|adc_sr[0] and I/O node IIU_MISO -- nodes have conflicting location assignments
Info (171110): Nodes could not be merged because their location constraints do not overlap

I am trying to force Quartus to use Fast Input Register on an input to my design using the Fast Input Register assignment. However, when I build my project I get the warnings in the code snippet. When I inspect the Resource Property Editor, I can see that Quartus has not used the IOB Fast Input Register.

Clearly there's something I'm not taking into account so how can I enable the Fast Input Register?

[sstrell]

What are your inputs connecting to?  If they are connecting to some hard resource on the device that has its own input registers, then you have a conflict between the use of the registers in the I/O cell and the registers in the hard resource.

If not that, do you have other physical location constraints, like Logic Lock regions?

[NJackson]

My input is connecting to a Shift Register instantiated using HDL.

There are no location constraints except for a pin assignment.

[AminT_Intel]

Hello,

Please check on this KDB: https://www.intel.com/content/www/us/en/support/programmable/articles/000081521.html

Thank you.

[AminT_Intel]

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