Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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16026 Discussions

Cyclone V SOC. Compiling the GHRD takes an insane amount of time


The mapper takes a lot of time to compile the Golden Hardware Reference Design for Cyclone V SOC. According to the messages it seems it is when it is generating the hard_block partition, which is essentially empty.


I'm using Quartus 17.0 free edition.


It doesn't seem to matter the actual design. Even reducing the design to the bare minimum. As long as the HPS is instantiated, it is enough produces the mapper to take so long at that stage.


Not sure if it is related to this, but why it is necessary to connect the HPS external signals to the pins on the top design. Is this only for the purpose of performing a timing analysis of the HPS?

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This is expected since you add HPS IP to your system, compilation might take long time.

Regarding the HPS pins, these pins are assigned from HPS IP in Platform Designer. They are needed to be exported to top-level, but no pin can be see as assigned, since they use dedicated Pins.

Timing wise, you might see that HPS pins are either clocks (need to define the clock only) or false path. In both cases, nothing will affect timing on HPS since this is Hard-core IP.