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I need a DDR interface for connecting a high speed DAC (DAC1627 from IDT/NXP). One of the DAC's two's channels gets it data with the risign edge, the other with the falling edge. I have 16 Bit data and clock, transmitted differential LVDS (one pair for each data and clock).
Is there any IP which could fit or other sample code?Link Copied
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You best use ALtera's ALTDDIO_OUT primitive; a 16-bit wide to drive the data and a 1-bit wide to drive the clock. Connect DataA to the datain_l port and DataB to the datain_h port of the 16-bit wide component. You connect "1" and "0" to the datain_h and datain_l of the 1-bit wide clock driver. So the clock to the DAC nicely arrives edge-aligned with the DDR data.
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Hi josyb,
thanks for your answer, great!
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