Hello,Can someone explain with real wolrd examples the difference between same edge transfers and opposite edge transfers in DDR input/output interface? Lets say there is external device with DDR interface which provides clk and data. For capturing data inside FPGA ALTDDIO_IN is used. How do I should determine what kind of false path exceptions to apply?
# For same edge transfers set_false_path -setup -rise_from -fall_to set_false_path -setup -fall_from -rise_to set_false_path -hold -rise_from -rise_to set_false_path -hold -fall_from -fall_to OR # For opposite edge transfers set_false_path -setup -rise_from -rise_to set_false_path -setup -fall_from -fall_to set_false_path -hold -rise_from -fall_to set_false_path -hold -fall_from -rise_to
Draw two waveforms one on top of the other, where the top one is the launch clock and the bottom one is the latch clock. Shift the bottom one to the right 90 degrees and you have a same-edge transfer, e.g. when a rising edge launches data, a rising edge latches it, and when a falling edge launches data, a falling edge latches it.Now do the same thing but shift the latch clock 90 degrees to the left(or the launch clock 90 degrees to the right, same thing). When a rising edge launches data, a falling edge latches it, and vice versa. This is opposite edge. That being said, I strongly recommend against adding the false paths. They don't help in any way and can only hurt. Let's go back to the same edge transfer example. When data is launched from the rising edge at time 0 degrees, it will be latched 90 degrees later by the rising edge capture flip-flop. But it will also be captured 270 degrees later by the falling edge flip-flop(these are two distinct paths and TQ will analyze both). The only thing the false-path does is cut that 270 degree setup transfer. But if you meet the more-restrictive and correct 90 degree transfer, then you've automatically met that much less restrictive rise->fall 270 degree transfer. So it doesn't help meet timing. But let's say you put the same edge transfer false paths in, but made a mistake as your setup is really opposite edge. In that case you're cutting the correct 90 degree transfer and leaving the incorrect 270 degree transrer. Your design will easily meet timing because you cut the correct, restrictive one. So there's pretty much nothing to gain and a lot to loose, so just leave them out. If you want to spend some time reading about it, I put together the following: http://www.alterawiki.com/uploads/e/ea/source_synchronous_timing.pdf#page=44
--- Quote Start --- That being said, I strongly recommend against adding the false paths. They don't help in any way and can only hurt. Let's go back to the same edge transfer example. --- Quote End --- Altera documentation clearly states that the default DDR behaviour of TimeQuest is that each launch edge is checked against the two latch edges. and that you must set false paths on irrelevant edges. There are plenty diagrams on that in document "source synchronous interfaces". This default behaviour is internal to the tool just like asynchronous clocks are assumed related unless you set otherwise. Obviously this is safe behaviour and in case of DDR the tool doesn't know which edge you are latching. As to the OP may Vlrean meant how to decide? That is matter of design. you can choose to capture same edge or opposite edges. When doing so you must take account of data order (odd/even).