I simulated the DDR2 controlor (IP core generate），Modelsim display :
# ** Error: F:/altera/72/modelsim_ae/win32aloem/../altera/verilog/src/cycloneii_atoms.v(5277): $hold( posedge clk &&& nosloadsclr:202410952 ps, datain:202410956 ps, 266 ps );# Time: 202410956 ps Iteration: 3 Instance: /easy_test_ddr2_top_tb/test/\ddr2_ddr_sdram|ddr2_auk_ddr_sdram_inst|ddr_io|g_datapath:4:g_ddr_io|g_dq_io:1:dq_io|auto_generated|input_cell_l[0]
Why?And how to solve ? Thank you!
