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Altera_Forum
Honored Contributor I
913 Views

DDR3 - Connecting 2 masters to one slave in QSYS

Hello, 

 

I have a DDR3 controller thats implemented in QSYS. 

The Avalon MM bus of the DDR3 has 2 masters connected to it: the ARM HPS and my custom logic.  

 

My question: 

 

Suppose the HPS issues a read request and the DDR3 controller fetches the data back after n clocks. 

Will the QSYS interconnect know that this data is intended only for the HPS - or will it also strobe the Avalon MM "read data valid" signal that's connected to the custom logic block ?  

 

In other words, 

When master A issue a read request and the slave answers - will master B see the answer ?
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Altera_Forum
Honored Contributor I
14 Views

Master B will not see the answer. 

 

I believe under some circumstances the 'readdata' might have the data destined for the other master, so you could maybe snoop it, but no, your custom logic 'readdatavalid' would not be asserted.