DDR3 MPFE timing constraints

[DBart1]

I am using the Cyclone V DDR3 IP core with hard memory controller and Uniphy. I am using multiple ports, using the MPFE feature, and the ports are clocked by unrelated clocks. Timequest is reporting timing failures between these clock domains however that originate at the HMC instance. I am confused though as the EMIF handbook says that "The FPGA fabric ports of the MPFE can be clocked at different frequencies. Synchronization is maintained by clock-domain crossing logic in the MPFE" so I dont understand why these paths wouldn't be cut by the IP cores's sdc file which cuts many other paths. If anyone who has experience working with the module to knows if these paths require being cut by the user please let me know

[NurAida_A_Intel]

Dear DBart1,

Thank you for joining this Intel Community. I am truly apologize for the delay in response due to long holiday in my region.

The issue you are facing is a known issue but it is not fix in the IP. As a workaround, we have published a KDB on how to cut the failing path in this link --> https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/solutions/rd08142014_213.html

Hope this helps.

Thanks

Regards,

NAli1

[DBart1]

Is the KDB mentioned somewhere in the User guide or other place that I missed? I am a little confused when using the IP what information is needed to be reviewed. There are 364 KDB articles that show up when search for DDR3. Why wouldn't this be mentioned in the IP User guide if it is a known issue?

[NurAida_A_Intel]

Hi DBart1,

The KDB is published after the IP released. In other word, the bug/issue were encountered after the IP released. The IP UG sometime is not updated anymore especially for old device. So, KDB page is use as the platform to update the user about the known issue.

I sincerely apologize for the inconvenience caused.

Regards,

NAli1