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DDR3 cannot read data when burst length larger than 8, Maximum Avalon-MM burst length set as 1024

Ryan-SEU
Novice
928 Views

Hi everyone, 
my work Environment : WIN10 64bits, Quartus II 18.1, modelsim-altera 10.5b, cyclone V E 5CEFA9F31I7N, Micron MT41J128M16JT-125*2.


Q1: I configured the Maximum Avalon-MM burst length=1024 of the avalon bus in the DDR3 IP Core. In the actual test, I found that if the read burst length is less than 8 (8 or 4), I can correctly write and Read the data(Fig1), but when the read burst length is greater than 8, the data cannot be read out(Fig2 write burstlength=16,read burstlength =8), in this case, I don't know whether the data is written to DDR3, why does this phenomenon occur? What are the possible reasons?

Attach the qar file.


Q2: I used two DDR3 chips, the number of chip selects should choose 1 or 2 ?(Fig3)

1.png

 Fig1

2.png

 Fig2

3.png

Fig3

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AdzimZM_Intel
Employee
905 Views

Hi Ryan,


Q1: If my understanding is right, it is referring to the width.

Also your memory has a Fixed burst length of 8 and burst chop of 4.


Q2: You use chip select of 2.


Regards,

Adzim


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Ryan-SEU
Novice
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Hi Adzim,

Q1: Thanks for your reply!what width do you mean?The data bit width of avalon has been set to 128bit.

Regards,

Ryan

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AdzimZM_Intel
Employee
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Hi Ryan,


I don't understand on the Fig 2 that you've shared.

The read burst length = 8 but rdatavalid is not asserted which I think there is no read transaction has performed.

If you set it to 16, what is the error occurred?



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AdzimZM_Intel
Employee
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We do not receive any response from you to the previous reply that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


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