hi folks,this is my first topic here and i was really stuck in this so please help me the problem started by having a DDC example from the Altera website and wanted to check it on my DSP Builder 7.1 but it was designed by 6.1 blocks so i did the conversion to the 7.1 but manually cause the automatic command line to upgrade didn't work for me and after great efforts in figuring out which is which in the modified parameters names i managed to complete the blocks but when i did press run i got an error that says: "illegal rate transition found involving 'm121/cic_clken' at input port 1 and 'm121/Constant' at output port 1. A Rate Transition must be inserted between them." not only one but many so i was just wondering what is the reason for this another thing i noticed the input or output ports have a new parameter called specify clock and clock (is this the reason of my problem ????) attached my model and work so please take a time in checking it out thanks for ur efforts
7.1 completely changed its simulation library and clocking schemes. Typically you now define your system clock rate with a Clock block. Set its rate to 'clock1' as your defined matlab variable. Name the clock block something. 'Clk1' will avoid confusion. Then define the sampling rates of all your inputs by setting their input clock rate to 'Clk1'. Note you need to use the Clock block name, not the Matlab variable.
Have you tried to use variable step of discrete solver in your simulation? From your .mdl design, browse to Simulation option, in Configuration Parameters, set Solver Type to Variable Step, Solver Discrete. Does that help?
This design example has been updated to 7.1SP1 release. You can find the updated example on http://www.altera.com/support/examples/dsp-builder/exm-dsp-builder.htmlIt says you need to have DSP Builder 7.1SP1, not just 7.1, for it to work. Good luck!