Decrypt verilog file

[Alexander_Kobler]

Hello,

How can I read an IEEE 1735 encrypted file (vendor specific key) into Quartus Pro 2021.3? 

The compiler outputs the following error messages:

Info: *******************************************************************
Info: Running Quartus Prime Synthesis
Info: Version 21.3.0 Build 170 09/23/2021 SC Pro Edition
Info: Processing started: Wed May 11 16:28:24 2022
Info: System process ID: 29918
Info: Command: quartus_syn --read_settings_files=on --write_settings_files=off counter -c counter
Info: qis_default_flow_script.tcl version: #1
Info: Initializing Synthesis...
Info: Project = "counter"
Info: Revision = "counter"
Info: Analyzing source files
Error (13223): Verilog HDL or VHDL error: No key to decrypt data block
Error (13223): Verilog HDL or VHDL error: decryption of data_block failed
Error (17390): Verilog HDL error at counter.vp(13): error in protected region near / File: counter.vp Line: 13
Error (13223): Verilog HDL or VHDL error: No key to decrypt data block in file counter.vp
Error (13223): Verilog HDL or VHDL error: decryption of data_block failed
Info (19551): Verilog HDL info at counter.vp(41): endmodule File: counter.vp Line: 41
Info (19551): Verilog HDL info at counter.vp(41): ^ File: counter.vp Line: 41
Error (13411): Verilog HDL syntax error at counter.vp(41) near text endmodule File: counter.vp Line: 41
Error (19645): Verilog HDL error at counter.vp(41): SystemVerilog keyword endmodule used in incorrect context File: counter.vp Line: 41
Error: Flow failed:

Thanks in advance & Best regards,

Alex

[ShengN_Intel]

Hi Alex,

If the design file is encrypted by third-party, probably have to get the IEEE 1735 specific encryption key for synthesis.

Thanks,

Best Regards

Sheng

[ShengN_Intel]

Alex,

If you already have the encryption key, do the followings:

1. Encrypt the design with IEEE 1735. Command line used: encrypt_1735 --quartus --language=verilog counter.v
2. File counter.vp will be generated in the file folder.
3. Open a new project, add counter.vp in the project. Set it as top-level entity.
4. Right click on the counter.vp. Select Properties. Ensure the Type: Verilog HDL File.
5. Run Analysis & Synthesis.

Best Regards,

Sheng

p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution and give Kudos.

[Alexander_Kobler]

Hi,

the file in the example was encrypted using Cadence' xmprotect, using IEEE 1735 encryption and a vendor specific key.  As Quartus Pro supports IEEE 1735 en/decryption as well, it should be possbile to compile the file with Quartus, or am I wrong?

Best regards,

Alex

[ShengN_Intel]

Hi Alex,

May check out this link https://www.intel.com/content/www/us/en/docs/programmable/683463/22-1/support-for-the-ieee-1735-encryption.html

Only file encryption with a third-party tool requires the public encryption key. File encryption with the Intel® Quartus® Prime Pro Edition software does not require the public encryption key.

Probably you have to get the public encryption key for encryption with third-party tool.

Best Regards,

Sheng

p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution and give Kudos.

[ShengN_Intel]

Hi Alex,

May I know any further update or concern?

Do you need further helps on this case?

Thank you.

Best Regards,

Sheng

[ShengN_Intel]

We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.