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Delaying signals

Altera_Forum
Honored Contributor II
‎08-29-2011 09:36 AM
1,071 Views

Hey, 

 

Firstly I'd like to mention that I'm a beginner in fpga programming :) 

 

I will use a simple example to show exactly what I'd like to know: 

 

(It turns out that I'm not allowed to post images or links so I used the Attach Files option) 

 

As you can see, when there's a rising edge on clk2, the clk0 hasn't yet changed it's state. 

 

What I would like to know is it possible to delay the clk2 signal so that when there's a rising edge on it, the clk0 had already changed. (Using TimeQuest analyzer!!!) 

 

I know that it's possible to set an offset to clk2 in the ALTPLL but I wanted to know is it possible to solve this problem TimeQuest Analyzer. 

 

I tried to set clock latency and net delay, etc but nothing seemed to work. I guess that I just don't understand everything right :) 

 

Hope that someone will help, 

Thanks in advance!
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Altera_Forum
Honored Contributor II
‎08-29-2011 10:03 AM
387 Views

dont go putting clocks through logic. That wont help and the skew will change with temperature and other factors. 

 

Use the delay on the PLL to phase shift a clock to the amount you need.
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