Demultiplexor Megafunction?

[Altera_Forum]

Hello, I am wondering if anybody created a custom megafunction that lets you make a demultiplexor. I am already aware that Altera provides a multiplexor megafunction, but it seems strange that they don't also have a demultiplexor too.

[Altera_Forum]

Are you using schematic entry or HDL?

[Altera_Forum]

I am currently using schematic design.

[Altera_Forum]

It's fairly easy to create your own demux using HDL. 

Quartus has an option to create a symbol from an HDL module, which you can then use in your design.  Here a small example in VHDL  library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity demux1_4 is port ( out0 : out std_logic; --output bit out1 : out std_logic; --output bit out2 : out std_logic; --output bit out3 : out std_logic; --output bit sel : in std_logic_vector(1 downto 0); bitin : in std_logic --input bit ); end demux1_4; architecture Behavioral of demux1_4 is begin process(bitin,sel) begin out0 <= '0'; out1 <= '0'; out2 <= '0': out3 <= '0'; case sel is when "00" => out0 <= bitin; when "01" => out1 <= bitin; when "10" => out2 <= bitin; when others => out3 <= bitin; end case; end process; end Behavioral;

[Altera_Forum]

Will this be the proper way to make a 2bit 4 output demultiplexor? 

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity demux2_4 is port ( out0 : out std_logic_vector(1 downto 0); --output bit out1 : out std_logic_vector(1 downto 0); --output bit out2 : out std_logic_vector(1 downto 0); --output bit out3 : out std_logic_vector(1 downto 0); --output bit sel : in std_logic_vector(1 downto 0); bitin : in std_logic_vector(1 downto 0); --input bit ); end demux2_4; architecture Behavioral of demux2_4 is begin process(bitin,sel) begin out0 <= '00'; out1 <= '00'; out2 <= '00': out3 <= '00'; case sel is when "00" => out0 <= bitin; when "01" => out1 <= bitin; when "10" => out2 <= bitin; when others => out3 <= bitin; end case; end process; end Behavioral;

[Altera_Forum]

Yes, it is. 

 ( darn, the forum requires at least 10 characters in posts... )

[Altera_Forum]

I tried compiling a 32 bit example of it, but I have an error: 

Error (10500): VHDL syntax error at testvhdl.vhd(12) near text ")"; expecting an identifier, or "constant", or "file", or "signal", or "variable"  I am not sure what the issue is, but all I did was take your code and edit it to be a 32bit demultiplexor. library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity demux32_4 is port ( out0 : out std_logic_vector(31 downto 0); --output bit out1 : out std_logic_vector(31 downto 0); --output bit out2 : out std_logic_vector(31 downto 0); --output bit out3 : out std_logic_vector(31 downto 0); --output bit sel : in std_logic_vector(31 downto 0); bitin : in std_logic_vector(31 downto 0); --input bit ); end demux32_4; architecture Behavioral of demux32_4 is begin process(bitin,sel) begin out0 <= '00000000000000000000000000000000'; out1 <= '00000000000000000000000000000000'; out2 <= '00000000000000000000000000000000': out3 <= '00000000000000000000000000000000'; case sel is when "00" => out0 <= bitin; when "01" => out1 <= bitin; when "10" => out2 <= bitin; when others => out3 <= bitin; end case; end process; end Behavioral;

[Altera_Forum]

the last entry in the port declaration should not have a ; on the end

[Altera_Forum]

Also (I missed it) std_logic_vector constants use "", not ''. 

 And you can replace out0 <= '00000000000000000000000000000000';with out0 <= (others => '0');to save some typing.

[Altera_Forum]

Here is a larger demultiplexor that I did that demultiplexes multiple inputs. I currently have the error : Error (10309): VHDL Interface Declaration error in testvhdl.vhd(77): interface object "signedmultiply1" of mode out cannot be read. Change object mode to buffer. Error (10327): VHDL error at testvhdl.vhd(77): can't determine definition of operator ""<="" -- found 0 possible definitions  

Here is the code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity alu_multiplicationordivisionchooser is port ( unsigneddivide0 : out std_logic_vector(31 downto 0); --output bit_vector unsigneddivide1 : out std_logic_vector(31 downto 0); --output bit_vector signeddivide0 : out std_logic_vector(31 downto 0); --output bit_vector signeddivide1 : out std_logic_vector(31 downto 0); --output bit_vector unsignedmultiply0 : out std_logic_vector(31 downto 0); --output bit_vector unsignedmultiply1 : out std_logic_vector(31 downto 0); --output bit_vector signedmultiply0 : out std_logic_vector(31 downto 0); --output bit_vector signedmultiply1 : out std_logic_vector(31 downto 0); --output bit_vector hiandlowregisterout : out std_logic_vector(63 downto 0); --output bit_vector gotoadder : out std_logic; --output bit subtract : out std_logic; --output bit sel : in std_logic_vector(2 downto 0); --input bit_vector busin0 : in std_logic_vector(31 downto 0); --input bit_vector busin1 : in std_logic_vector(31 downto 0); --input bit_vector hiandlowregisterin : in std_logic_vector(63 downto 0) --input bit_vector ); end alu_multiplicationordivisionchooser; architecture Behavioral of alu_multiplicationordivisionchooser is begin process(busin0,busin1,sel) begin unsigneddivide0 <= (others => '0'); unsigneddivide1 <= (others => '0'); unsignedmultiply0 <= (others => '0'); unsignedmultiply1 <= (others => '0'); signeddivide0 <= (others => '0'); signeddivide1 <= (others => '0'); signedmultiply0 <= (others => '0'); signedmultiply1 <= (others => '0'); hiandlowregisterout <= (others => '0'); gotoadder <= '0'; subtract <= '0'; case sel is when "000" => signedmultiply0 <= busin0, signedmultiply1 <= busin1; when "001" => unsignedmultiply0 <= busin0, unsignedmultiply1 <= busin1; when "010" => signeddivide0 <= busin0, signeddivide1 <= busin1; when "011" => unsigneddivide0 <= busin0, unsigneddivide1 <= busin1; when "100" => signedmultiply0 <= busin0, signedmultiply1 <= busin1, hiandlowregisterout <= hiandlowregisterin ,gotoadder <= '1' ; when "101" => unsignedmultiply0 <= busin0, unsignedmultiply1 <= busin1, hiandlowregisterout <= hiandlowregisterin ,gotoadder <= '1'; when "110" => signedmultiply0 <= busin0, signedmultiply1 <= busin1, hiandlowregisterout <= hiandlowregisterin, gotoadder <= '1', subtract <= '1'; when others => out3 <= unsignedmultiply0 <= busin0, unsignedmultiply1 <= busin1, hiandlowregisterout <= hiandlowregisterin ,gotoadder <= '1', subtract <= '1'; end case; end process; end Behavioral;   I am guessing the issue I have is with the case, and how I tell it to assign multiple outputs a value at the same time.  EDIT: Nevermind I figured out the issue. I had to replace: case sel is when "000" => signedmultiply0 <= busin0, signedmultiply1 <= busin1; when "001" => unsignedmultiply0 <= busin0, unsignedmultiply1 <= busin1; when "010" => signeddivide0 <= busin0, signeddivide1 <= busin1; when "011" => unsigneddivide0 <= busin0, unsigneddivide1 <= busin1; when "100" => signedmultiply0 <= busin0, signedmultiply1 <= busin1, hiandlowregisterout <= hiandlowregisterin ,gotoadder <= '1' ; when "101" => unsignedmultiply0 <= busin0, unsignedmultiply1 <= busin1, hiandlowregisterout <= hiandlowregisterin ,gotoadder <= '1'; when "110" => signedmultiply0 <= busin0, signedmultiply1 <= busin1, hiandlowregisterout <= hiandlowregisterin, gotoadder <= '1', subtract <= '1'; when others => out3 <= unsignedmultiply0 <= busin0, unsignedmultiply1 <= busin1, hiandlowregisterout <= hiandlowregisterin ,gotoadder <= '1', subtract <= '1'; end case;  With: case sel is when "000" => signedmultiply0 <= busin0; signedmultiply1 <= busin1; when "001" => unsignedmultiply0 <= busin0; unsignedmultiply1 <= busin1; when "010" => signeddivide0 <= busin0; signeddivide1 <= busin1; when "011" => unsigneddivide0 <= busin0; unsigneddivide1 <= busin1; when "100" => signedmultiply0 <= busin0; signedmultiply1<= busin1; hiandlowregisterout <= hiandlowregisterin; gotoadder <= '1' ; when "101" => unsignedmultiply0 <= busin0; unsignedmultiply1 <= busin1; hiandlowregisterout <= hiandlowregisterin; gotoadder <= '1'; when "110" => signedmultiply0 <= busin0; signedmultiply1 <= busin1; hiandlowregisterout <= hiandlowregisterin; gotoadder <= '1'; subtract <= '1'; when others => unsignedmultiply0 <= busin0; unsignedmultiply1<= busin1; hiandlowregisterout <= hiandlowregisterin; gotoadder <= '1'; subtract <= '1'; end case;