Design Compilation Report: Performance Results

[Altera_Forum]

I am using Intel FPGA SDK for OpenCL to compile my OpenCL design as follows: 

  aoc -v --board a10gx my_kernel.cl -o my_kernel.aocx --report  In the report I found board utilization estimates and latency for separate blocks.  How can I get results for precise board utilization, overall latency, interval, and power?

[Altera_Forum]

Board utilization --> Check acl_quartus_report.txt after full placement-and-routing. 

Overall latency --> If you mean the cumulative latency of all the pipelines, you can just calculate the sum of the latency values from the report. If you want something else, clarify. Interval --> I am not sure what you mean by this. Power --> Precise power usage can only be obtained by running the kernel on an actual board and either reading the power sensor from the board (if available) or using a PCI-E extender alongside with external power meters. Power estimations can be obtained by using Quartus PowerPlay on the project that is created by the OpenCL compiler.

[Altera_Forum]

--- Quote Start ---  Board utilization --> Check acl_quartus_report.txt after full placement-and-routing. Overall latency --> If you mean the cumulative latency of all the pipelines, you can just calculate the sum of the latency values from the report. If you want something else, clarify. Interval --> I am not sure what you mean by this. Power --> Precise power usage can only be obtained by running the kernel on an actual board and either reading the power sensor from the board (if available) or using a PCI-E extender alongside with external power meters. Power estimations can be obtained by using Quartus PowerPlay on the project that is created by the OpenCL compiler.  --- Quote End ---    What about simple Quartus II projects? I figured out how to use TimeQuest Timing Analyzer to calculate maximum frequency but I couldn't find anything on how to get latency metrics.

[Altera_Forum]

--- Quote Start ---  What about simple Quartus II projects? I figured out how to use TimeQuest Timing Analyzer to calculate maximum frequency but I couldn't find anything on how to get latency metrics.  --- Quote End ---    If you are talking about HDL projects, you can calculate the latency manually by counting the number of register in your pipeline, and dividing that by post-place-and-route operating frequency.