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Honored Contributor I
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Design Unit Not Found

Hello all, 

 

I'm still trying to get my *first* simulation running with ModelSim, and my progress is quite limited. I think I have my license issues worked out finally, after talking directly to Altera support. 

 

Currently, I am trying to run simulations on my project, but am getting errors. whenever I try to simulate anything (right click on module in my work dir and select simulate), I get the following: 

 

ModelSim> vsim work.TX_PLL# vsim work.TX_PLL # Start time: 17:52:30 on Mar 09,2016# Loading work.TX_PLL# ** Error: (vsim-3033) D:/Users/Nicholai/Desktop/Research/QuartusII/March2016/DACSimulation/TX_PLL.v(75): Instantiation of 'altpll' failed. The design unit was not found.# Time: 0 ps Iteration: 0 Instance: /TX_PLL File: D:/Users/Nicholai/Desktop/Research/QuartusII/March2016/DACSimulation/TX_PLL.v# Searched libraries:# D:/Users/Nicholai/Desktop/Research/QuartusII/March2016/DACSimulation/simulation/modelsim/rtl_work# Error loading design# End time: 17:52:31 on Mar 09,2016, Elapsed time: 0:00:01# Errors: 1, Warnings: 0 

 

I found a lot of threads with similar problems, but haven't figure out the solution. I am not sure where the library for 'altpll' is. I do have a huge list of libraries in the library pane. Is there an easy way to know what library my cores are from? Once I figure out what library altpll is in, when do I use the include directory command? Should that go in my .do file? Not a single one of my modules will simulate- I am using: 

 

ROM: 1-Port 

LPM_COUNTER 

ALTDIDO_OUT 

ALTPLL 

 

I am using a Stratix IV device. 

 

Sorry if this is a very easy question to answer, I have never used this tool (or hardly any Altera tools) before. Right now, I have nothing set up and working. I'd like to get to the point where I have a testbench. 

 

Thank you, 

FrenchyRaoul
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Honored Contributor I
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Hello, 

 

Let's try to first solve issue with ALTPLL. You should be able to solve it by adding following library : altera_lnsim_ver. Does this name appear in your list of libraries? 

 

Now, question is where to add this? If you are using do file then, following command should help. vsim -L <library_name>. This -L command is used to search library for design units instantiated from Verilog and for VHDL default component binding. 

 

Please try this item and be relaxed. We should be able to solve this. 

 

Have a Good Day! 

 

Bhaumik
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Honored Contributor I
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As what Bhaumik pointed out, you might be missing some libraries or simulation models. 

 

Try to find the required files at your $QUARTUS_ROOTDIR/quartus/eda/sim_lib folders. 

 

Probably you need: 

1. altera_mf.v 

2. altera_lnsim.sv 

3. stratixiv_atoms.v 

 

You will need to compile the above files together before running simulation.
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--- Quote Start ---  

As what Bhaumik pointed out, you might be missing some libraries or simulation models. 

 

Try to find the required files at your $QUARTUS_ROOTDIR/quartus/eda/sim_lib folders. 

 

Probably you need: 

1. altera_mf.v 

2. altera_lnsim.sv 

3. stratixiv_atoms.v 

 

You will need to compile the above files together before running simulation. 

--- Quote End ---  

 

 

Thank you. I checked, and all three of this files are present. 

 

 

--- Quote Start ---  

Hello, 

 

Let's try to first solve issue with ALTPLL. You should be able to solve it by adding following library : altera_lnsim_ver. Does this name appear in your list of libraries? 

 

Now, question is where to add this? If you are using do file then, following command should help. vsim -L <library_name>. This -L command is used to search library for design units instantiated from Verilog and for VHDL default component binding. 

 

Please try this item and be relaxed. We should be able to solve this. 

 

Have a Good Day! 

 

Bhaumik 

--- Quote End ---  

 

 

Thank you. This name does appear in my list of libraries (along with the other two that were mentioned mikedsouze). I tried right clicking on the component and selecting 'Simulate', and it failed as expected. I then added the flags you suggested, but it appears that I am having the same issue? 

 

ModelSim> vsim -L altera_lnsim_ver work.TX_PLL# vsim -L altera_lnsim_ver work.TX_PLL # Start time: 19:59:37 on Mar 10,2016# Loading work.TX_PLL# ** Error: (vsim-3033) D:/Users//Desktop/Research/QuartusII/March2016/DACSimulation/TX_PLL.v(75): Instantiation of 'altpll' failed. The design unit was not found.# Time: 0 ps Iteration: 0 Instance: /TX_PLL File: D:/Users//Desktop/Research/QuartusII/March2016/DACSimulation/TX_PLL.v# Searched libraries:# C:/altera/15.1/modelsim_ae/altera/verilog/altera_lnsim# D:/Users//Desktop/Research/QuartusII/March2016/DACSimulation/simulation/modelsim/rtl_work# Error loading design# End time: 19:59:37 on Mar 10,2016, Elapsed time: 0:00:00# Errors: 1, Warnings: 0
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Honored Contributor I
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Hello FrenchyRaoul, 

 

First, you have been able to add that library in your search path. ( See "C:/altera/15.1/modelsim_ae/altera/verilog/altera_lnsim" in your message. Modelsim looked into that path. ) That's good. 

 

Second, sorry my mistake. 'allpll' is not a part of library I mentioned previously. So, please add following library ( altera_mf_ver ) in same way you added altera_lnsim_ver. 

 

 

--- Quote Start ---  

Thank you. I checked, and all three of this files are present. 

--- Quote End ---  

 

As mikedsouze mentioned, you need to COMPILE them.Just presence of those files at above location is not enough. (I think this is alternative way. That is you can either compile these files or you can add libraries using vsim -L. ) 

 

Hope to be able to solve at least issue with 'altpll'. If it works, then for other modules you may also need to add other libraries in following way.( vsim -L altera_mf_ver -L alter_lnsim_ver )  

 

Cheers, 

Bhaumik
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Honored Contributor I
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--- Quote Start ---  

Hello FrenchyRaoul, 

 

First, you have been able to add that library in your search path. ( See "C:/altera/15.1/modelsim_ae/altera/verilog/altera_lnsim" in your message. Modelsim looked into that path. ) That's good. 

 

Second, sorry my mistake. 'allpll' is not a part of library I mentioned previously. So, please add following library ( altera_mf_ver ) in same way you added altera_lnsim_ver. 

 

 

As mikedsouze mentioned, you need to COMPILE them.Just presence of those files at above location is not enough. (I think this is alternative way. That is you can either compile these files or you can add libraries using vsim -L. ) 

 

Hope to be able to solve at least issue with 'altpll'. If it works, then for other modules you may also need to add other libraries in following way.( vsim -L altera_mf_ver -L alter_lnsim_ver )  

 

Cheers, 

Bhaumik 

--- Quote End ---  

 

 

Bhaumik, you've been very helpful so far. I ran the following: 

 

ModelSim> vsim -L altera_mf_ver work.TX_PLL# vsim -L altera_mf_ver work.TX_PLL # Start time: 16:49:04 on Mar 17,2016# Loading work.TX_PLL# Loading altera_mf_ver.altpll# Loading altera_mf_ver.ALTERA_DEVICE_FAMILIES# Loading altera_mf_ver.pll_iobuf# Loading altera_mf_ver.MF_stratixiii_pll# Loading altera_mf_ver.ttn_m_cntr# Loading altera_mf_ver.ttn_n_cntr# Loading altera_mf_ver.ttn_scale_cntr 

 

This 'worked', and opened up a simulation! Cool! 

 

Okay, so, moving forward, I want to be able to simulate my top level file. Here is what my .do file looks like: 

 

transcript onif {} { vdel -lib rtl_work -all } vlib rtl_work vmap work rtl_work vlog -vlog01compat -work work +incdir+D:/Users//Desktop/Research/QuartusII/March2016/DACSimulation {D:/Users//Desktop/Research/QuartusII/March2016/DACSimulation/dac_top.v} vlog -vlog01compat -work work +incdir+D:/Users//Desktop/Research/QuartusII/March2016/DACSimulation {D:/Users//Desktop/Research/QuartusII/March2016/DACSimulation/signalROM_verilog.v} vlog -vlog01compat -work work +incdir+D:/Users//Desktop/Research/QuartusII/March2016/DACSimulation {D:/Users//Desktop/Research/QuartusII/March2016/DACSimulation/daccounter_verilog.v} vlog -vlog01compat -work work +incdir+D:/Users//Desktop/Research/QuartusII/March2016/DACSimulation {D:/Users//Desktop/Research/QuartusII/March2016/DACSimulation/ALTDDIO_CLK_OUT.v} vlog -vlog01compat -work work +incdir+D:/Users//Desktop/Research/QuartusII/March2016/DACSimulation {D:/Users//Desktop/Research/QuartusII/March2016/DACSimulation/ALTDDIO_TX.v} vlog -vlog01compat -work work +incdir+D:/Users//Desktop/Research/QuartusII/March2016/DACSimulation {D:/Users//Desktop/Research/QuartusII/March2016/DACSimulation/TX_PLL.v} vlog -vlog01compat -work work +incdir+D:/Users//Desktop/Research/QuartusII/March2016/DACSimulation {D:/Users//Desktop/Research/QuartusII/March2016/DACSimulation/dataclk_pll.v} vlog -vlog01compat -work work +incdir+D:/Users//Desktop/Research/QuartusII/March2016/DACSimulation/db {D:/Users//Desktop/Research/QuartusII/March2016/DACSimulation/db/tx_pll_altpll.v} vlog -vlog01compat -work work +incdir+D:/Users//Desktop/Research/QuartusII/March2016/DACSimulation/db {D:/Users//Desktop/Research/QuartusII/March2016/DACSimulation/db/dataclk_pll_altpll.v}  

 

How can I tell my .do file where to look for the library? Is it the same -L flag for the vlog command? Hopefully I'm moving in the right direction. If I want to have a testbench, or be able to simulate my top level module using a fake simulated clock, can this be done in a .do file? I'm sorry for getting off topic, but you've been very helpful so far.
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Honored Contributor I
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Hello, 

 

Thank you for your kind words. Whenever I am in trouble, someone on this forum helps me, so I am just trying do same. And I am glad that it is helpful to you. 

 

Anyway, let get back to our topic. 

 

vlog command compiles Verilog source code and SystemVerilog extensions into a specified working library while vsim command invokes the VSIM simulator. Consider tb_test is your test bench TOP file. In this case, first you need to compile this using vlog command. ( In the same way you are compiling your dac_top.v and other files.) Then you can use following command : vsim -L altera_mf_ver work.tb_test. 

 

Let us know whether it works or not. 

 

Cheers, 

Bhaumik
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Honored Contributor I
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--- Quote Start ---  

Hello, 

 

Thank you for your kind words. Whenever I am in trouble, someone on this forum helps me, so I am just trying do same. And I am glad that it is helpful to you. 

 

Anyway, let get back to our topic. 

 

vlog command compiles Verilog source code and SystemVerilog extensions into a specified working library while vsim command invokes the VSIM simulator. Consider tb_test is your test bench TOP file. In this case, first you need to compile this using vlog command. ( In the same way you are compiling your dac_top.v and other files.) Then you can use following command : vsim -L altera_mf_ver work.tb_test. 

 

Let us know whether it works or not. 

 

Cheers, 

Bhaumik 

--- Quote End ---  

 

 

Bhaumik, I think I am getting closer. Thank you. 

 

I decided to create a TestBench file. To do so, I used: 

 

Processing -> Start... -> Start Test Bench Template Writer 

 

This gave me a .vht file titled dac_top.vht. Next, I went to: 

 

Assignments -> Settings... -> EDA Tool Settings -> Simulation -> Test Benches... 

 

I created a new test bench titled 'dac_top_tb', and Top level module in test bench = 'dac_top_tb'. I added this file to the project as well.  

 

My .do file was automatically updated with a new vsim line, which includes all of the proper libraries: 

 

vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L stratixiv_hssi_ver -L stratixiv_pcie_hip_ver -L stratixiv_ver -L rtl_work -L work -voptargs="+acc" dac_top_tb add wave * view structure view signals run -all 

 

However, now I am getting a very similar answer to before- however, I don't know what library my test bench is in?  

 

# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L stratixiv_hssi_ver -L stratixiv_pcie_hip_ver -L stratixiv_ver -L rtl_work -L work -voptargs=""+acc"" dac_top_tb# Start time: 16:16:42 on Mar 22,2016# ** Error: (vsim-3170) Could not find 'D:/Users//Desktop/Research/QuartusII/March2016/DACSimulation/simulation/modelsim/rtl_work.dac_top_tb'.# # Error loading design 

 

Can you see what I am doing wrong?
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Honored Contributor I
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Hello, 

 

Error message says Modelsim is unable to find out 'dac_top_tb' module. It looks like you have not compiled 'dac_top_tb' module using vlog command before running vsim command. Have you? If not, please do that and let us know what happens. 

 

Cheers, 

Bhaumik
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Honored Contributor I
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--- Quote Start ---  

Hello, 

 

Error message says Modelsim is unable to find out 'dac_top_tb' module. It looks like you have not compiled 'dac_top_tb' module using vlog command before running vsim command. Have you? If not, please do that and let us know what happens. 

 

Cheers, 

Bhaumik 

--- Quote End ---  

 

 

Hmm. So I tried to vlog the test bench, but this is the output: 

 

VSIM(paused)> vlog D:/Users//Desktop/Research/QuartusII/March2016/DACSimulation/simulation/modelsim/dac_top.vht# Model Technology ModelSim ALTERA vlog 10.4b Compiler 2015.05 May 27 2015# Start time: 15:41:11 on Mar 25,2016# vlog -reportprogress 300 D:/Users//Desktop/Research/QuartusII/March2016/DACSimulation/simulation/modelsim/dac_top.vht # ** Error: (vlog-13036) D:/Users//Desktop/Research/QuartusII/March2016/DACSimulation/simulation/modelsim/dac_top.vht(1): near "--": Operator only allowed in SystemVerilog.# # ** Error: (vlog-13069) D:/Users//Desktop/Research/QuartusII/March2016/DACSimulation/simulation/modelsim/dac_top.vht(1): near "--": syntax error, unexpected --, expecting class.# # End time: 15:41:11 on Mar 25,2016, Elapsed time: 0:00:00# Errors: 2, Warnings: 0# C:/altera/15.1/modelsim_ae/win32aloem/vlog failed. 

 

Does vlog work on vht test bench files normally? I used the testbench creator tool, which gave me the .vht. They are using "--" to denote comment lines.
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Hello, 

 

 

--- Quote Start ---  

Does vlog work on vht test bench files normally? 

--- Quote End ---  

 

 

No. .vht stands for VHDL test bench file while vlog command compiles Verilog source code and SystemVerilog source codes. Hence it will not work.  

 

You should try following : 

  1. In Quartus, Go to Assignments -> Settings... -> EDA Tool Settings -> Simulation. 

    In that select 'Verilog' under 'Format for Output Netlist'. 

  2. In Quartus, Go to Processing -> Start... -> Start Test Bench Template Writer 

    This should now create dac_top.vt file in same folder in which dac_top.vht file was being created before. 

  3. Now try following command: vlog -reportprogress 300 D:/Users/
 

 

We would like to know what happens with this. 

 

Thank you, 

Bhaumik
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Or you could do vcom on dac_top.vht?

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--- Quote Start ---  

Hello, 

 

 

 

No. .vht stands for VHDL test bench file while vlog command compiles Verilog source code and SystemVerilog source codes. Hence it will not work.  

 

You should try following : 

  1. In Quartus, Go to Assignments -> Settings... -> EDA Tool Settings -> Simulation. 

    In that select 'Verilog' under 'Format for Output Netlist'. 

  2. In Quartus, Go to Processing -> Start... -> Start Test Bench Template Writer 

    This should now create dac_top.vt file in same folder in which dac_top.vht file was being created before. 

  3. Now try following command: vlog -reportprogress 300 D:/Users/
 

 

We would like to know what happens with this. 

 

Thank you, 

Bhaumik 

--- Quote End ---  

 

 

Bhaumik, you have proven yourself very helpful (and generous) with your help. I think I am very close to having a working test bench. Here is the output of your steps: 

 

vlog -reportprogress 300 D:/Users//Desktop/Research/QuartusII/March2016/DACSimulation/simulation/modelsim/dac_top.vt# Model Technology ModelSim ALTERA vlog 10.4b Compiler 2015.05 May 27 2015# Start time: 21:03:15 on Mar 28,2016# vlog -reportprogress 300 D:/Users//Desktop/Research/QuartusII/March2016/DACSimulation/simulation/modelsim/dac_top.vt # -- Compiling module dac_top_vlg_tst# # Top level modules:# dac_top_vlg_tst# End time: 21:03:16 on Mar 28,2016, Elapsed time: 0:00:01# Errors: 0, Warnings: 0
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@ mikedsouze, 

Thank you for sharing idea about vcom command. It could have solved problem more easily. 

 

@ FrenchyRaoul, 

We are glad to hear that you are close to your goal. 

 

Cheers, 

Bhaumik
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Another possible cause of this error is when you have your top level name and the corresponding file name different from the module name .

For example,
TOP_LEVEL_NAME=testbench, corresponding file name=testbench.sv.
module you declared inside testbench.sv=module testbench_top;.

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