Diagnosing Congestions

[NickFritzsche]

Hello,

our Arria 10 design suffers from routing congestions.

We used the "Top Congested Nets" report to identify critical nets and reworked the design, e.g. by manual register replication, pipelining etc.

Despite the elimination of several high-fan-out nets, routing still fails with congestions.

Since we have seen designs containing nets with significantly higher number of overused nodes and fan-outs, we are questioning our metrics.

How can we diagnose the root cause of router congestions?

Please find attached the archived project.

Best regards, NickFritzsche

[RichardTanSY_Intel]

Hi,

Please allow me some time to investigate your design.

I appreciate your patience while I look into this for you.

Regards,

Richard Tan

[RichardTanSY_Intel]

Your design is having routing congestion on both short and long wire.

Short Wire:

You might need to reduce the number of wire in your RTL design, starting with the highest Total Grid Length shown on the Global Router Wire Utilization Map. To view the RTL design files, right-click the nodes in the Global Router Wire Utilization Map > Locate nodes > Locate in Design Files. Then you can check which wire that can reduced, based on your design need. 

Long Wire:

Additionally, you may consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
This will disable optimization of problematic paths and expose them for further analysis using the Timing Analyzer.

Regards,

Richard Tan

[RichardTanSY_Intel]

Hi,

Dropping a note to ask if my last reply was helpful to you.

Do you able to resolve the issue? 

Regards,

Richard Tan

[NickFritzsche]

Hi Richard,

thank you for analyzing the design and providing strategies to address short and long wire routing congestion.

We have replaced the firmware blocks responsible for most of the short wire routing congestion with alternative implementations. As a result, the compilation now completes without congestion errors or timing violations.

However, we are surprised to see that the long wire routing hotspot map still displays large and intense hotspots (see below).

Based on the hotspot maps, we initially assumed that improving long wire utilization was necessary, but the successful compilation suggests otherwise. Could you clarify how we should interpret the long wire utilization hotspot map to make informed design improvements?

We are currently analyzing short wire utilization and will follow up with further questions next week.

Best regards,

Nick Fritzsche

[RichardTanSY_Intel]

The Global Router Wire Utilization Map and the chip planner gives a visual representation of estimated wire usage on the chip and give detailed information about what might be causing the route congestion.

If the compilation passed and there is no timing violation, there should not be any concern with the routing congestion.

If you want to continue optimize the design, you may checkout the user guide below.

Reference:

https://www.intel.com/content/www/us/en/docs/programmable/683641/24-3/viewing-routing-congestion-in-chip-planner.html

Regards,

Richard Tan

[RichardTanSY_Intel]

Let me know if you need further assistance.

Regards,

Richard Tan

[RichardTanSY_Intel]

We noticed that we haven't received a response from you regarding the latest previous question/reply/answer, and will now transitioning your inquiry to our community support. We apologize for any inconvenience this may cause and we appreciate your understanding.

If you have any further questions or concerns, please don't hesitate to reach out. Please login to https://supporttickets.intel.com/s/?language=en_US, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

The community users will be able to help you on your follow-up questions.

Thank you for reaching out to us!

Best Regards,

Richard Tan