Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
15663 Discussions

Difference between logic elements mentioned in flow summary and synthesis summary

sidd
Novice
203 Views

After compiling RTL, we get compilation report. In compilation report we get Flow summary, Analysis and synthesis summary. Both reports are giving me different number of logic elements used. What is the difference between two? LEs used has to be a same number in both reports right? 

I have compiled for MAXV device. 

MAX V CPLD programming specifications 

0 Kudos
1 Solution
sstrell
Honored Contributor III
194 Views

The final numbers to use are in the Fitter section of the compilation report.  Any numbers from an earlier stage of compilation are estimates and usage before final Fitter optimizations.

View solution in original post

3 Replies
sstrell
Honored Contributor III
195 Views

The final numbers to use are in the Fitter section of the compilation report.  Any numbers from an earlier stage of compilation are estimates and usage before final Fitter optimizations.

sidd
Novice
183 Views

Thanks @sstrell  for reply.

I have one more question.

What percentage of LEs ideally shall be used ? Any impact on performance if more than 90% of LEs are used?

 

sstrell
Honored Contributor III
159 Views

It depends on the design.  There's no ideal percentage.  It may not be so much the performance as it is the Fitter's ability to fit a large design in the device while still meeting the timing requirements.

Reply