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Novice
165 Views

Disable Quartus timing analyzer inverted clock

Hello,

Is there a way to disable the inverted clock latch analysis in quartus 20.1 for arria 10?

I had no such inverted clock analysis with the same design using Quartus 13.1 on stratix 3

, with similar sdc constraints (and design was running fine on board).

Timings are very bad with this inverted clk analysis (gated clock on falling edge).

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12 Replies
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Valued Contributor III
160 Views

Re: Disable Quartus timing analyzer inverted clock

Can you post your SDC?  This is pretty strange.  It also looks like all the failures are on paths that are fanning in to a single clock enable input which seems odd.  Can you post any of the HDL for this part of the design?

#iwork4intel

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Novice
156 Views

Re: Disable Quartus timing analyzer inverted clock

I cannot share RTL code.

 

I use this kind of constraints for now to remove those timing checks:

 

set_false_path -fall_to [get_clocks {mcu_clk}] -from [get_registers {*|u_rfd_clockshop|i_apb_if|s_sw_all_periph_reset_en}]


set_false_path -rise_from [get_clocks {mcu_clk}] -to [get_registers {*|u_flash_subsys|A_ip_pflash640k_atfc|u_controller|u_fmc_if|start_gate|u_cgate|ClkEnable*}]

 

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Novice
154 Views

Re: Disable Quartus timing analyzer inverted clock

Here is the SDC.

For this run, variables are set to:

$is_a_quartus_only_project == "0"

$current_project == "Achilles_arria_X"

$is_a_quartus_project == "1"

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Highlighted
Moderator
133 Views

Re:Disable Quartus timing analyzer inverted clock

You need to look into your rtl viewer whether the launch and latch clock make sense. set false path will remove the analysis but it might cause functional failure if those path are valid analysis.


If you can provide us a rtl screenshot on those path will be good.


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Novice
119 Views

Re: Re:Disable Quartus timing analyzer inverted clock

Quartus 20.1/arria 10 had too hard time to analyze the design with the test logic (test mode can then be enabled or not based on an input pin).

There was no issue with Quartus 13.1/stratix 3 FPGA.

I have the impression that Quartus 20.1 checks much more timings than Quartus 13.1 was (expecially those inverted checks).

At the moment I disabled/removed the test logic to ease quartus place and route.

 

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Moderator
106 Views

Re:Disable Quartus timing analyzer inverted clock

yes, there should have a lot improvement done compare to the old quartus. You will have to analyze whether this make sense from your side. Or you can send us your design to have a look.


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Moderator
90 Views

Re:Disable Quartus timing analyzer inverted clock

any update?


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Highlighted
Novice
86 Views

Re: Re:Disable Quartus timing analyzer inverted clock

My colleague mentioned to me that he's not surprised that there are much more hold timing violations for smaller device node (arria 10 vs stratix 3).

Can you confirm that it is more difficult to achieve positive hold slack on arria 10 devices compare to stratix 3 for example?

 

 

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Highlighted
Moderator
59 Views

Re:Disable Quartus timing analyzer inverted clock

We can't confirm on this. As we do not do benchmark for old device e.g. Stratix III.


What you can do is open up the timing analyzer to do the comparison. It should show you all the details there.


I would suggest you attend the timing closure class as well. Look into the prerequisite before attending the timing closure class, as you might need to know on timing analyzer as well.


https://www.intel.com/content/www/us/en/programmable/support/training/course/odswtc02.html

Thanks


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Novice
30 Views

Re: Re:Disable Quartus timing analyzer inverted clock

Finally got it timing clean (fixes hold time violation on arria 10 with quartus 20.2) using other settings,

see attached file.

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Highlighted
Novice
23 Views

Re: Re:Disable Quartus timing analyzer inverted clock

And the qsf settings according it.

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Highlighted
Novice
15 Views

Re: Re:Disable Quartus timing analyzer inverted clock

Unfortunately the bad hold timing violation plague is back using a new netlist of synplify pro.

I don't know what quartus is doing anymore.

Why is it adding +12 ns mlab routing all around the fpga ...

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