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Altera_Forum

Honored Contributor I

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10-29-2017
02:39 PM

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Dividing a negative number

Hi

How can I divide a negative number by 32 ? without using a dsp ip core. thanksLink Copied

5 Replies

Altera_Forum

Honored Contributor I

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10-29-2017
03:49 PM

46 Views

By dividing the number by 32...

Division by a power of two is simply removing that many LSBs from the number, it takes no combinational logic what-so-ever. 32 is 2^5, so you need only remove the lower 5 bits of the number and the division is done. If you want the output width to stay the same, then for a signed number, simply replicate the MSB to fill the gap.```
{{(5){a}},a}
```

Where "MSB" is the width-1 of the signal you are dividing. Alternatively, do an arithmetic shift: ```
$signed(a)>>>5
```

Will do the same thing. The examples I gave are in Verilog. I realise this is the VHDL forum, but I am not familiar with the language. There will be an equivalent in VHDL.
Altera_Forum

Honored Contributor I

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10-29-2017
04:41 PM

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the easiest way, would just be a divide. divide by 2^n infers a bit shift.

```
signal ip, s : signed(31 downto 0);
s <= ip / 32;
```

Altera_Forum

Honored Contributor I

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10-30-2017
07:40 AM

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this is what I did in VHDL: what do you think?

1.shift right 5 bits. 2.fill this 5MSBs slope(10 downto 0) <= delta_y (15 downto 5) ; slope(15 downto 11) <= delta_y(15) & delta_y(15) & delta_y(15) & delta_y(15) & delta_y(15);
Altera_Forum

Honored Contributor I

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10-30-2017
08:13 AM

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It will work just fine. Is there any reason you dont want to use the signed data type? then you wouldnt need to pad the sign bit as you can use the resize function:

slope <= resize( delta_t(15 downto 5), slope'length);
Altera_Forum

Honored Contributor I

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11-03-2017
09:53 PM

46 Views

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