Does Altera have equivalent of Xilinx "ASYNC_REG" attribute?

[Altera_Forum]

In Xilinx, there is an Attribute "ASYNC_REG" that can be applied to registers that have D inputs that are asynchronous to the clock domain - usually CDC registers. This attribute has the effect of placing these registers in the same SLICE to minimise the routing and reduce the chance of metastability in the crossing. 

 I cannot find an equivalent, or work out a way to do it for Stratix IV. We have common CDC code that uses this register and in Xilinx compiles we can put a max_delay constraint of 1/2 of a clock between the sync registers without a problem. In Quartus, it never manages to meet this timing constraint. I usually have to go back to old habits of setting of false pathing the inputs to the CDC (usually done via a max delay of 1 or 2 clocks to prevent the registers being too far apart).   Can you force quartus to place registers in the same ALUT, or As close as physically possible?  ASYNC_REG attribute is described here: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_2/ug912-vivado-properties.pdf

[Altera_Forum]

--- Quote Start ---  In Xilinx, there is an Attribute "ASYNC_REG" that can be applied to registers that have D inputs that are asynchronous to the clock domain - usually CDC registers. This attribute has the effect of placing these registers in the same SLICE to minimise the routing and reduce the chance of metastability in the crossing.  I cannot find an equivalent, or work out a way to do it for Stratix IV. We have common CDC code that uses this register and in Xilinx compiles we can put a max_delay constraint of 1/2 of a clock between the sync registers without a problem. In Quartus, it never manages to meet this timing constraint. I usually have to go back to old habits of setting of false pathing the inputs to the CDC (usually done via a max delay of 1 or 2 clocks to prevent the registers being too far apart).   Can you force quartus to place registers in the same ALUT, or As close as physically possible?  ASYNC_REG attribute is described here: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_2/ug912-vivado-properties.pdf  --- Quote End ---    I have always relied on Altera doing that for me :) I expected Xilinx to do likewise, oops :( Quartus automatically detects the synchroniser chains in your design; the only caveat is that the two clocks must have been constrained as exclusive in a set_clock_groups command in the sdc-file. You can read all about this in the quartus manual (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/qts/qts-qpp-5v1.pdf): page 914 ff. There is an option in the Settings menu to specify the (minimum?) length of the synchroniser chain