Does Quartus II support use of fixed point arithmatic packages in VHDL?

[Altera_Forum]

The question is result of what I have read here from Sep 2011: 

https://www.altera.com/support/support-resources/knowledge-base/solutions/rd12082010_811.html Is this still true for Quartus in Nov 2016?   Is it correct that fixed point arithmatic can be implemented using std_logic_vectors as long as a person is careful about shifting the bits correctly and truncating them correctly to fit in with the required fixed point format? If so, what is the purpose of the VHDL packages fixed_generic_pkg and fixed_pkg? Are the types sfixed and ufixed defined in them synthesizeable by Quartus? Are there any specific instructions on how to use these fixed point types from these packages in Quartus?

[Altera_Forum]

Yes, it is still true, and the packages are finally included with Q15.1 prime pro. If you dont have a pro licence, you'll have to provide the '93 compatible versions from off the web. 

The advantage is it makes fixed point much clearer in your code:  signal f : sfixed(1 downto -14);  You shouldnt be using std_logic_vector at all to represent integers. You should only be using it to connect to IP blocks that require it, otherwise you should be using numeric_std with signed/unsigned or the fixed_pkg ufixed/sfixed. VHDL does not define any arithmatic for std_logic_vectors.

[Altera_Forum]

hmm, if I can use sfixed and ufixed then how is it true to say that fixed point is not support like it says in the Altera website link?? 

If fixed point library was created in '93 then why is it not in Quartus II yet?? What changed in '2008 that was not true in previous versions when it comes to fixed point support?  I have used numeric_std a lot and always use the unsigned and signed for arithmatic or sometimes and integer. However, I only found this week that there is something called sfixed and ufixed. Since I found it out so very late, I am sure that there are some good reasons why these are not ubiquitous.   I get the impression that mankind has used std_logic_vector to implement fixed point calculations and just shifted and truncated the bits as required. People use some seperate variable or constant to store the information about the fractional and whole part. Perhaps this is a good place to use a VHDL "record".

[Altera_Forum]

The fixed_pkg was added to VHDL 2008. David Bishop created a version that was compatible with VHDL '93 and has most of the features of the 2008 version, but is not part of the VHDL standard so users have to "use it at their own risk". Many people have used it succesfully however, including me. Quartus has only just started supporting the official 2008 version from Version 15.1 pro. 

 Nothing is different in the underlying hardware. There is nothing you can do with the fixed_pkg you cannot do with numeric_std. Its just a more convenient way of coding.

[Altera_Forum]

Thanks for the help