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15334 Discussions

Does Quartus supports Dynamic Array declaration?

Altera_Forum
Honored Contributor II
1,365 Views

Hi, 

 

I was wondering anyone here knows whether the Altera Quartus II supports SystemVerilog's new Dynamic Array Declaration, which allows run-time array dimension reconfigruation? 

 

For example, 

 

reg [7:0] array[]; 

 

array = new[4]; 

array = new[8](array); 

 

which allows we dynamically change the dimension of the array at run-time. I have tried to compile the code in Quartus II 15.0 and 13.0.sp1, but get errors. Anybody can help? 

 

Thanks, 

 

-Roger
0 Kudos
8 Replies
Altera_Forum
Honored Contributor II
484 Views

No 

FPGAs are not software. And dynamically alocating hardware in runtime would not be possible. 

These constructs are for testing and verification purposes only.
PPerd2
Novice
385 Views
You are not right. Dynamic arrays can be used, for example, when calculating parameters that can define the structure of a project.
PPerd2
Novice
381 Views
You are not right. Dynamic arrays can be used, for example, when calculating parameters that can define the structure of a project during compilation.
Altera_Forum
Honored Contributor II
484 Views

I've been confused and frustrated with this as well. Sure, you wouldn't use dynmic arrays in implemented FPGA designs, but like you said a good chunk of the System Verilog constructs are there to support test benching and verification, and who doesn’t need to test or verify their FPGA designs? From what I can gather ModelSim had support in it years ago for dynamic arrays and most of the SV definition. So is it just the Altera version that doesn't support these features of SV?

Altera_Forum
Honored Contributor II
484 Views

As mentioned, there's a difference between synthesis and simulation. You can't dynamically change hardware while it's running (except when using an advanced feature, like partial reconfiguration). You can do and test anything you want in simulation, even if it can't be synthesized. HDLs were originally designed for simulation, so there's lots of stuff you can do in these languages that can't be synthesized.

Altera_Forum
Honored Contributor II
484 Views

I agree, but the question remains? Why doesn't the Altera version of ModelSim support those features of System Verilog that are there for simulation-only?

Altera_Forum
Honored Contributor II
484 Views

Dynamic arrays work just fine for me in modelsim altera 10.3d (the one from Q15). 

Are you compiling the code with the -sv switch, or is the file a .sv file? .v files will default to Verilog, which does not support dynamic arrays. 

 

Code I used: 

 

module dyn_test; initial begin logic dyna ; dyna = new; dyna = {0, 1, 2, 3}; foreach(dyna) $display("%2h", dyna); dyna = new({dyna, 4,5,6,7}); foreach(dyna) $display("%2h", dyna); end endmodule
Altera_Forum
Honored Contributor II
484 Views

Thanks Tricky!  

 

I was making an embarrassingly newbie mistake. I didn’t have my new[] statement in a procedural block. I’m very glad it was my mistake and not a limitation of the tool though (I'm using ModelSim Altera 10.3c from Q14.1 with both the .sv extension and the -sv switch).
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