Does the compiler add or omitted unused gates ?

[Altera_Forum]

For example, if I had a 74244 buffer, and only used 4 buffers, and I do not connected the other 4 buffers to anything, would the compiler still add those unused gates into the PLD logic blocks ? Or would the compiler just omit them to save on gates used in the PLD ?

[Altera_Forum]

With an FPGA/CPLD, you're not implementing a component, like an old TI part, in the device. You are creating buffers and logic that are implemented using device resources. So if you have 4 buffers in a design, logic resources for 4 buffers will be implemented in the device.

[Altera_Forum]

Yes, It will implement all the logic blocks written in FPGA/CPLD irrespective of whether it is used in program. 

In other words, it is a open net.    Best Regards, Tzi Khang, Lim (This message was posted on behalf of Intel Corporation)

[Altera_Forum]

--- Quote Start ---  Yes, It will implement all the logic blocks written in FPGA/CPLD irrespective of whether it is used in program. In other words, it is a open net.  Best Regards, Tzi Khang, Lim (This message was posted on behalf of Intel Corporation)  --- Quote End ---    This is not my experience. The compiler is smart enough to remove logic that is not used logically, so large portions of logic that for example drive a node that is never used may be optimized out of the design. Likewise, if some large block of logic ends up generating a constant result, it can be optimized down to a constant.  There are directives available that can be attached to signals / nodes in the source that specify that the attached node NOT be removed, but rather preserved, but this is the not the default. The compiler will aggressively remove unused logic unless explictly told not to by user directives.

[Altera_Forum]

I believe that ak6dn is correct and will note this is the second time I've seen limtzikhang give faulty advice. What does (This message was posted on behalf of Intel Corporation) mean?

[Altera_Forum]

--- Quote Start ---  This is not my experience. The compiler is smart enough to remove logic that is not used logically, so large portions of logic that for example drive a node that is never used may be optimized out of the design. Likewise, if some large block of logic ends up generating a constant result, it can be optimized down to a constant.  There are directives available that can be attached to signals / nodes in the source that specify that the attached node NOT be removed, but rather preserved, but this is the not the default. The compiler will aggressively remove unused logic unless explictly told not to by user directives.  --- Quote End ---    Hi,  1.Yes compiler will omit the unused signals & block which have no connection logically to the Entity/module ports which can be seen in RTL viewer/also we can see it in chip planner LAB & LE.  2.But if we have unused ports in entity/module it will be a open net.  Please correct me if i'm wrong.  Thanks Hari

[Altera_Forum]

--- Quote Start ---  Hi,  1.Yes compiler will omit the unused signals & block which have no connection logically to the Entity/module ports which can be seen in RTL viewer/also we can see it in chip planner LAB & LE.  2.But if we have unused ports in entity/module it will be a open net.  Please correct me if i'm wrong.  Thanks Hari  --- Quote End ---    Once the design is compiled and fitted, there is no longer any concept of a block or module; everything has been flattened/smashed to just a bunch of logic.  So (2) is not quite correct; unused output ports of modules will have the logic driving them removed. There will never by any dangling unused outputs by default (unless the user specifically adds the compiler directives to preserve a specific node). Logic driving unused output ports of modules will be pruned back until all the nodes are used as an input to some cell.  It is not the case that entire modules are either included or removed; this optimization is pushed down to the individual logic cell level.  Not quite sure what you are trying to convey in point (1).